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| 09:00 - 10:00 | Keynote Speech
Model to Hardware Matching for nm Scale Technologies
Sani
Nassif, IBM, USA
Chair: Lars Svensson, Chalmers Univ., Gotenburg, Sweden
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| 10:30 - 12:00 | Paper Session 3: Arithmetic and memories.
Session Chair: Armin Tajalli, EPFL, Lausanne, Switzerland
Mixed radix-2 and high-radix RNS bases for lowpower multiplication
Ioannis Kouretas, Vassilis Paliouras - Univ. of Patras, Greece
Power Optimization of Parallel Multipliers in Systems with Variable Word-length
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Lars Lundheim, Asghar Havashki -
Norwegian Univ. of Science and Technology, Norway
A Design Space Comparison of 6T and 8T SRAM Core-Cells
Florian Bauer, Georg Georgakos - Infineon Technologies AG, Germany
Doris Schmitt-Landsiedel - Technische Univ. Müchen, Germany
Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization
Yan Li, Doris Schmitt-Landsiedel - Technische Univ. München, Germany
Helmut Schneider, Florian Schnabel, Roland Thewes - Qimonda AG, Germany
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| 13:30 -
15:30 | Paper Session 4: Variability and statistical timing.
Session Chair: L. Miguel Silveira, INESC-ID / IST, TU Lisbon, Portugal
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic
Massimo Alioto - Univ. of Siena, Italy
Gaetano Palumbo, Melita Pennisi - Univ. of Catania, Italy
A Study on CMOS Time Uncertainty with Technology Scaling
Monica Figueiredo - IPL/ESTG, Portugal
Rui Aguiar - Univ. de Aveiro, Portugal
Static Timing Model Extraction for Combinational Circuits
Bing Li, Christoph Knoth, Manuel Schmidt, Walter Schneider, Ulf Schlichtmann - TU München, Germany
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA
Walter Schneider, Manuel Schmidt, Bing Li, Ulf Schlichtmann - TU München, Germany
Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power
Howard Chen, Scott Neely, Jinjun Xiong, Vladimir Zolotov and Chandu Visweswariah - IBM, USA
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| 16:00 - 17:30 |
Paper Session 5: Synchronization and interconnect.
Session Chair: Massimo Alioto, Univ. Siena, Italy
Logic Synthesis of Handshake Components using Structural Clustering Techniques
Francisco Fernández, Josep Carmona - Univ. Politécnica de Catalunya, Spain
Fast Universal Synchronizers
Rostislav Dobkin, Ran Ginosar - Technion, Israel
A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router
Tsung-Yi Ho - National Cheng Kung University, Taiwan
PMD: A Low-power Code for Networks-on-Chip based on Virtual Channels
Alberto Garcia-Ortiz - Anafocus, Spain
Leandro Indrusiak, Tudor Murgan - TU Darmstadt, Germany
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