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Power and Profit: Engineering in the Envelope
Ted Vucurevich, Cadence

Abstract: A convergence of opportunities and concerns has driven consumer and industrial buying behavior to put increasing value on electronic systems which offer significantly differentiated capabilities in the area of Power Effectiveness. As a direct result of this, engineering teams from Systems through Material Science have been motivated to drive the development of new capabilities that allow effective design of complex, power optimized systems. This keynote will explore the challenges and possible solutions for Engineering in the Envelope of these power optimized systems.

Ted Vucurevich serves as a Cadence Chief Technology Officer, reporting to Michael J. Fister, President and CEO. He is responsible for driving advanced research and development and directing Cadence Laboratories. In addition, he serves as an executive fellow. In his prior role as chief architect at Cadence, Vucurevich helped develop the strategies and technology initiatives in system-on-a-chip (SoC)-based design, DSM infrastructure, software interoperability, design methodology development, and Internet-based electronic system design. Vucurevich joined Cadence in 1992 as director of the Analog Physical Design group. In 1994 he was promoted to work as an architect in the Viper Development group. He was later named chief architect and held that position for five years. Prior to Cadence, Vucurevich worked 14 years at Analog Devices where he held roles in product, design, and computer-aided design (CAD) engineering. He was a co-founder of the Linear Signal Processing Division, where he was responsible for the implementation of a complete mixed-signal ASIC CAD environment. Vucurevich received his bachelor of science degree in electrical engineering from the University of Arizona.

Model to Hardware Matching for nm Scale Technologies
Sani Nassif, IBM

Abstract: Our ability to reliably predict the outcome of a semiconductor manufacturing process has been steadily deteriorating. This is happening because of two important factors.

  • First, the overall CMOS technology slowdown has led to rapidly increasing complexity in the process and in its interaction with design. This has in turn caused an increase in the number and magnitude of systematic sources of mismatch between simulation models (both at the circuit simulation and timing levels) and hardware measurements.
  • Second, manufacturing variability -long a source of concern only for analog design- is becoming important for digital designs as well and thus its prediction is now a first order priority. However, it is competing for the attention of researchers and CAD developers with a host of other so-called nm effects, thus slowing down the delivery of needed solutions.

The result is (a) our ability to arbitrarily compose a design out of disparate components is compromised because of a high degree of interaction between these components , and (b) our ability to predict the nominal performance of a design as well as its tolerances and sensitivities is in danger. Phenomena like SRAM stability and leakage power variations are the first of many problems we are facing at 65nm and below.

In this talk, we will review these issues and show how they are all related to the core issue of model to hardware matching. We will also show examples of potential solutions to this problem some of which are currently being developed in IBM, and some which are longer term and would benefit greatly from the attention of the academic community.

Sani Nassif is Manager of the Tools and Technology Department at IBM Austin Research Laboratory. Sani received his PhD from Carnegie-Mellon university in the eighties. He worked for ten years at Bell Laboratories on various aspects of design and technology coupling including device modeling, parameter extraction, worst case analysis, design optimization and circuit simulation. He joined the IBM Austin Research Laboratory in January 1996 where he is presently managing the tools and technology department, which is focused on design/technology coupling and includes activities in: model to hardware matching, simulation and modeling, physical design, statistical modeling, statistical technology characterization and similar areas.

Integration of Power Management Units onto the SoC
Floriberto Lima, Chipidea - MIPS

Abstract: SoC complexity has increased exponentially adding new requirements to power management. To manage power dissipation and increase battery autonomy developers need to have flexible control over the supply of the multiple SoC power domains. Requirements include: supply voltages much lower than those available from the main supply; fine voltage programming, complex power sequencing; and very fast load response. All with high power conversion efficiency. External IC solutions make it difficult to comply with SoC performance and functional requirements, and result in a large BOM. Developers should consider flexible power management IP that can integrate onto their SoC or SiP to optimize performance, power efficiency, cost and size.

Floriberto Lima is Technical Marketing Manager of the Analog Business Group - Chipidea, MIPS Technologies, Inc. As Marketing Manager Floriberto Lima is responsible for the road map and product definition of Power Management Solutions at MIPS Technologies. He joined Chipidea in 2000 as Design Manager for Portable Power Management and subsequently became Engineering Manager for Power Management System Architecture. Prior to joining Chipidea, Floriberto was R&D Engineer at Instituto de Telecomunicações, in Lisbon, where he developed Active Power Filter topologies. Floriberto received the MSc degree in Electrical and Computers Engineering from IST, Technical University of Lisbon and MBA degree in General Management from Universidade Católica Portuguesa and Universidade Nova de Lisboa.