Power and Profit: Engineering in the Envelope
Ted Vucurevich - Cadence Design Systems, USA

Chair: L. Miguel Silveira, INESC-ID / IST, TU Lisbon, Portugal

Session Chair: Howard Chen, IBM, Yorktown-Heights, NY, USA

Near-field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits
Thomas Ordas - LIRMM / STMicroelectronics, France
Mathieu Lisart - STMicroelectronics, France
Philippe Maurine, Lionel Torres - LIRMM, France
Etienne Sicard - INSA - LESIA, France

A comparison between two logic synthesis forms from the digital switching noise viewpoint
Giorgio Boselli, Valentina Ciriani, Valentino Liberali, Gabriella Trucco - Univ. of Milano, Italy

Generating Worst-Case Stimuli for Accurate Power Grid Analysis
Pedro Morgado, Paulo Flores, José Monteiro - INESC-ID / TU Lisbon, Portugal
L. Miguel Silveira - Cadence Labs / INESC-ID / TU Lisbon, Portugal

Monolithic Multi-Mode DC-DC Converter with Gate Voltage Optimization
Nuno Dias - IST, Portugal
Marcelino Santos - IST / INESC-ID, Portugal
Floriberto Lima, Chipidea MIPS, Portugal
Beatriz Borges - IST / IT, Portugal
Júlio Paisana - IST, Portugal

Session Chair: Kostas Siozios, Democritus Univ. Thrace, Greece

Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements
Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija - Univ. of California - Davis, USA

A New Dynamic Logic Circuit Design for an Effective Trade-off between Noise-Immunity, Performance and Energy Dissipation
Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo - Univ. of Calabria - DEIS, Italy

Energy Efficient Elliptic Curve Processor
Maurice Keller and William Marnane - Univ. College Cork, Ireland

Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing
Marco Lanuzza, Stefania Perri, Pasquale Corsonello - Univ. of Calabria - DEIS, Italy
Martin Margala - Univ. of Massachusetts Lowell, USA

Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures
D. Kissler, A. Strawetz, Frank Hannig, J. Teich - Univ. of Erlangen-Nuremberg, Germany

Session Chair: Jorge Juan, Univ. Sevilla, Spain

Analytical High-level Power Model for LUT-based Components
Ruzica Jevtic - Universidad Politecnica de Madrid, Spain
Carlos Carreras - LSI-DIE-ETSIT, Spain

A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption
Gustavo Callou, Paulo Maciel, Ermeson Carneiro, Bruno Nogueira, Eduardo Tavares, Meuse Oliveira Júnior - Univ. Federal of Pernambuco, Brazil

Power dissipation associated to internal effect transitions in static CMOS gates
Alejandro Millan, Jorge Juan Chico, Manuel J. Bellido, David Guerrero, Paulino Ruiz-de-Clavijo, Julian Viejo - Univ. de Sevilla, Spain

Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level
Felipe Machado, Teresa Riesgo, Yago Torroja - Univ. Politecnica de Madrid, Spain

Data Dependence of Delay Distribution for a Planar Bus
Francesc Moll, Joan Figueras, Antonio Rubio - Univ. Politecnica de Catalunya, Spain

Organized by: João Cardoso - IST/UTL/INESC-ID Lisboa, Portugal

Techniques for Power Optimized FPGA Design: Novel Approaches towards Power Reduction for Future Tool Supported Design Automation
Rob Esser, Juanjo Noguera - Xilinx Inc., Ireland
Jürgen Becker, Michael Hübner, Katarina Paulsson - Universität Karlsruhe, Germany

Smart enumeration: a systematic approach to exhaustive search
Tim Todman, Gabriel Coutinho, Wayne Luk, Oskar Mencer - Imperial College, UK

A Power-Aware Placement and Routing Algorithm Targeting to 3D FPGAs
K. Siozios, D. Soudris - Thrace Democritus University, Greece

Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor
Mladen Berekovic - TU Braunschweig, Germany
Tom Vanderaa - IMEC, Belgium
Frank Bouwens - IMEC-NL, The Netherlands