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08:30 - 09:00 | Registration |
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09:00 - 09:20 | Opening Session |
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09:20 - 10:10 | Keynote Speech
Integration of Power Management Units onto the SoC Floriberto Lima -
Chipidea MIPS, Portugal
Chair: Marcelino Santos, INESC-ID / IST, TU Lisbon, Portugal
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10:30 - 12:00 |
Paper Session 1: Low-leakage and subthreshold circuits.
Session Chair: Yngvar Berg, Oslo University, Norway
Subthreshold FIR Filter Architecture for Ultra Low
Power Applications
Biswajit Mishra, Bashir Al-Hashimi - Univ. of Southampton, UK
Reverse Vgs Static
CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations
in Sub-threshold Designs
Bahman Kheradmand Boroujeni, Christian Piguet - CSEM, Switzerland
Yusuf Leblebici - EPFL, Switzerland
Improving the Power-Delay Performance in
Subthreshold Source-Coupled Logic Circuits
Armin Tajalli, Yusuf Leblebici - EPFL, Switzerland
Massimo Alioto - Univ. of Siena, Italy
Elizabeth J. Brauer - Northern Arizona Univ., USA
Design and evaluation of mixed 3T-4T FinFET stacks for leakage reduction
Matteo Agostinelli, David Esseni, Luca Selmi - DIEGM, Univ. of Udine, Italy
Massimo Alioto - Univ. of Siena, Italy
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13:30 - 15:30 |
Paper Session 2: Low-power methods and models.
Session Chair: René van Leuken, TU Delft, The Netherlands
Temporal Discharge Current Driven Clustering for Improved Leakage Power
Reduction in Row-Based Power-Gating
Ashoka Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino -
Politecnico di Torino, Italy
Luca Benini - Univ. of Bologna, Italy
Intelligate: Scalable Dynamic Invariant Learning for Power
Reduction
Roni Wiener -
Gila Kamhi - Intel Corp., Israel
Moshe Vardi - Rice Univ., USA
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus
Power Consumption
Masanori Muroyama, Masaki Yamaguchi, Tohru Ishihara, Hiroto Yasuura -
Kyushu Univ., Japan
Power-Aware Design via Micro-Architectural Link to
Implementation
Yoni Aizik, Gila Kamhi, Yael Zbar, Hadas Ronen, Muhammad Abozaed - Intel
Corp., Israel
Untraditional Approach to Computer Energy Reduction
Vasily Moshnyaga - Fukuoka Univ., Japan
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15:30 - 16:00 |
Poster Session 1: Circuits and methods.
Session Chair: Philippe Maurine, LIRMM, Montpellier, France
Settling-Optimization-Based Design Approach for Three-stage Nested-Miller Amplifiers
Andrea Pugliese, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo - Univ. of Calabria, Italy
Ultra Low Voltage High Speed Differential CMOS Inverter
Omid Mirmotahari, Yngvar Berg - Univ. of Oslo, Norway
Differential Capacitance Analysis
Marco Bucci, Raimondo Luzzi - Infineon Technologies AG, Germany
Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti - Univ. of Rome La Sapienza, Italy
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey
Martin Simlastik, Viera Stopjakova - Slovak Univ. of Technology, Slovakia
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses
Antoine Courtay - Lab-STICC / IRISA, France
Johann Laurent - UBS/Lab-STICC, France
Olivier Sentieys - IRISA, France
Nathalie Julien - LESTER, France
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Transportation to Reception Venue |
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