CV: Joan Figueras obtained his doctoral degree at the UPC and his PhD and MsC degrees from the University of Michigan (Ann Arbor Mich.USA). He is currently Professor at the Electronics Engineering Dpt. of the Universitat Politècnica de Catalunya in Barcelona, Spain. His research interests are centered in emerging topics in low power design and advanced test of electronic circuits and systems.

The impact of leakage power and its relative incidence in the total power consumption will be analyzed. The main contributions to leakage and their physical nature will be presented. The dependence of subthreshold, gate and junction leakages on the device geometry, materials and temperature will be introduced and possible strategies to control its impact on the leakage power consumption at device and circuit level will be discussed.

CV: Enrico Macii holds a Dr.Eng. degree in electrical engineering and the Ph.D. degree in computer engineering from Politecnico di Torino, and the Dr.Sc. degree in computer science from Università di Torino. Currently, he is a Full Professor at the Politecnico di Torino. His research interests include several aspects of the computer-aided design of digital integrated circuits and systems, with particular emphasis on the development of methodologies, algorithms and tools for power estimation and optimization of systems described at various levels of the design hierarchy.

The second part of the Tutorial will cover high level techniques to control leakage power. Power gating strategies based on Sleep Transistor Insertion (STI) will be discussed showing different solutions for the interfacing of sleep regions (Voltage Anchor Circuits). Leakage power in SRAM and CACHE memories will be presented with techniques to control leakage power. Finally, architectural techniques such as Adaptive Body Bias (ABB), Adaptive Voltage Scaling (AVS), and combinations of ABB&AVS will be shown and its efficiency discussed.

CV: Kaushik Roy received the B.Tech. degree from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, TX. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, where he is currently a Professor and University Faculty Scholar. His research interests include VLSI design/CAD for nanoscale silicon and non-silicon technologies, low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing.

Transistors are becoming leakier every technology generation and to add to the problem, process parameter variations is making the leakage spread to be significant. In this talk I will explore the implications of current and new device technology and architecture on leakage current and the leakage spread, and possible circuit and architecture level solutions to deal with the problem.

CV: Manoj Sachdev is a University Research Chair professor in Electrical and Computer Engineering department at the University of Waterloo, Canada. His research interests include low power, high speed circuit design; test and manufacturing issues of integrated circuits. He has contributed to five books, more than 150 technical papers, and holds more than 25 granted and pending patents.

Embedded SRAMs often occupy vast majority of the total area of modern System on Chips (SoCs). Embedded SRAMs significantly impacts power, performance, testability and yield of complex SoCs. In this presentation, salient design challenges and design techniques will be discussed to reduce leakage as well as active power consumption while maintaining data stability in nano-metric SRAMs.

CV: Tudor Murgan studied between 1996 and 2001 at the Faculty of Electronics and Communications at the University "Politehnica" of Bucharest, Romania and received in 2006 the PhD title from the Darmstadt Univ. of Technology in Germany. Currently he works for Qimonda AG in Munich, and his interests and main working fields include low-power and high-speed circuit design, statistical methods for CAD, and interconnect modeling and optimization.

Since nowadays power consumption and especially the leakage-induced one represent potential limits for technology scaling, it is of utmost importance to shift the estimation accuracy typical for low abstraction layers to higher ones. This talk focuses on stochastic techniques - and their applicability and accuracy - that can be employed to efficiently estimate power consumption early in the design flow, i.e. at architectural and system level.