Luís Guerra e Silva's home page

Topics

My research interests are focused on efficient algorithms and data structures for solving electronic design automation problems. My current research work consists in the study and development of efficient models and algorithms for timing analysis of ICs under process variations, an important issue in the latest nanometric IC technologies. In the past I did some research work in the application of boolean satisfiability algorithms (SAT) to EDA problems, namely timing analysis and ATPG. Other unrelated topics of interest include: pervasive computing, data mining, cryptography and internet-related technologies.

Patents

Luis Guerra e Silva, L. Miguel Silveira and Joel Phillips, "Branch and Bound Techniques for Computation of Critical Timing Conditions", U.S. Patent 8,245,167, issued August 2012.

Publications

Ricardo Barata, Sergio Silva, Luis Cruz and Luis Guerra e Silva, "Open APIs in Information Systems for Higher Education". In European University Information Systems Conference (EUNIS), Umea, Sweden, June, 2014.

Ricardo Marques, Luis Guerra e Silva, Paulo F. Flores and L. Miguel Silveira, "Improving SAT Solver Efficiency Using a Multi-Core Approach". In Proceedings of the Twenty-Sixth International Florida Artificial Intelligence Research Society Conference (FLAIRS), pp. 94-99, St. Pete Beach, FL, May 2013.

Debjit Sinha, Luis Guerra e Silva, Jia Wang, Shesha Raghunathan, Dileep Netrabile and Ahmed Shebaita, "TAU 2013 Variation Aware Timing Analysis Contest". In Proceedings of the ACM International Symposium on Physical Design (ISPD), pp. 171-178, The Ridge Tahoe, Stateline, NV, March 2013.

Luis Guerra e Silva, "Unifying Functional and Parametric Timing Verification". In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 135-140, Salt Lake City, UT, May 2012.

Luis Guerra e Silva and L. Miguel Silveira, "Handling Intra-Die Variations in PSTA". In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 403-406, Lausanne, Switzerland, May 2011.

Luis Guerra e Silva, Joel R. Phillips and L. Miguel Silveira, "Speedpath Analysis Under Parametric Timing Models". In Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 268-273, Anaheim, CA, June 2010.

Luis Guerra e Silva, Joel R. Phillips and L. Miguel Silveira, "Effective Corner-Based Techniques for Variation-Aware IC Timing Verification". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 1, January 2010.

Luis Guerra e Silva, Zhenhai Zhu, Joel R. Phillips and L. Miguel Silveira, "Library Compatible Variational Delay Computation". In IFIP International Federation for Information Processing, Volume 249, VLSI-SoC: Research Trends in VLSI and Systems on Chip, G. De Micheli, S. Mir and R. Reis, Editors, pp 157-176, Springer, January 2008.

Luis Guerra e Silva, Joel Phillips and L. Miguel Silveira, "Efficient Computation of the Worst-Delay Corner". In Proceedings of the IEEE/ACM Design, Automation and Test in Europe Conference (DATE), Nice, France, April 2007.

Luis Guerra e Silva, Joel Phillips and L. Miguel Silveira, "Efficient Computation of the Exact Worst-Delay Corner". In IEEE/ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Austin, TX, February 2007.

Luis Guerra e Silva, Zhenhai Zhu, Joel Phillips and L. Miguel Silveira, "Variation-Aware, Library Compatible Delay Modeling Strategy". In Proceedings of the Fourteenth International Conference on Very Large Scale Integration (VLSI-SoC 2006), Nice, France, October 2006. Best paper award.

Luis Guerra e Silva, Afshin Abdollahi, Philip Chong, Christoph Albrecht, Joel Phillips and Andreas Kuehlmann, "OpenAccess Gear Timing". Invited talk at the 8th OpenAccess+ Conference, Santa Clara, California, April 2006.

João Marques-Silva and Luis Guerra e Silva, "Solving Satisfiability in Combinational Circuits", in IEEE Design and Test of Computers, pp. 16-21, July-August 2003.

C. Visweswariah, A. R. Conn and L. G. Silva, "Exploiting Optimality Conditions in Accurate Static Circuit Tuning", G. Di Pillo and A. Murli, Editors, High Performance Algorithms and Software for Nonlinear Optimization, Kluwer Academic Publishers, Dordrect, The Netherlands, pp. 356-374, 2003.

Luis Guerra e Silva, João Marques-Silva, L. Miguel Silveira and Karem A. Sakallah, "Satisfiability Models and Algorithms for Circuit Delay Computation", in ACM Transactions on Design Automation of Electronic Systems, Vol. 7, No. 1, pp. 137-158, January 2002.

João P. Marques-Silva and Luis Guerra e Silva, "Algorithms for Satisfiability in Combinational Circuits Based on Backtrack Search and Recursive Learning", in Proceedings of the XII Symposium on Integrated Circuits and Systems Design (SBCCI), Natal, Brasil, September/October 1999

Luis Guerra e Silva, "Models and Algorithms for Timing Analysis of Combinational Circuits", Master Thesis, Instituto Superior Técnico, Lisboa, Portugal, June 1999.

João P. Marques-Silva and Luis Guerra e Silva, "Algorithms for Satisfiability in Combinational Circuits Based on Backtrack Search and Recursive Learning", in IEEE/ACM International Workshop on Logic Synthesis (IWLS), Lake Tahoe, California, June 1999.

Luis Guerra e Silva, João Marques-Silva and L. Miguel Silveira, "Algorithms for Solving Boolean Satisfiability in Combinational Circuits", in Proceedings of the IEEE/ACM Design, Automation and Test in Europe Conference (DATE), Munich, Germany, March 1999.

Luis Guerra e Silva, João Marques-Silva, L. Miguel Silveira and Karem A. Sakallah, "Timing Analysis Using Propositional Satisfiability", in Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS), Lisboa, Portugal, September 1998.

Luis Guerra e Silva, João Marques-Silva, L. Miguel Silveira and Karem A. Sakallah, "Realistic Delay Modeling in Satisfiability-Based Timing Analysis", in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, California, May 1998.

Luis Guerra e Silva, João Marques-Silva, L. Miguel Silveira and Karem A. Sakallah, "Satisfiability Models and Algorithms for Circuit Delay Computation", in Proceedings of the ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Austin, Texas, December 1997.

Software

CGRASP: A structure-aware version of the widely known satisfiability checker GRASP. It is intended to be used in solving satisfiability problems derived from combinational logic circuits (ATPG, CEC, CDC, etc).

	Ricardo Barata, Sergio Silva, Luis Cruz and Luis Guerra e Silva, "Open APIs in Information Systems for Higher Education". In European University Information Systems Conference (EUNIS), Umea, Sweden, June, 2014.
	Ricardo Marques, Luis Guerra e Silva, Paulo F. Flores and L. Miguel Silveira, "Improving SAT Solver Efficiency Using a Multi-Core Approach". In Proceedings of the Twenty-Sixth International Florida Artificial Intelligence Research Society Conference (FLAIRS), pp. 94-99, St. Pete Beach, FL, May 2013.
	Debjit Sinha, Luis Guerra e Silva, Jia Wang, Shesha Raghunathan, Dileep Netrabile and Ahmed Shebaita, "TAU 2013 Variation Aware Timing Analysis Contest". In Proceedings of the ACM International Symposium on Physical Design (ISPD), pp. 171-178, The Ridge Tahoe, Stateline, NV, March 2013.
	Luis Guerra e Silva, "Unifying Functional and Parametric Timing Verification". In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 135-140, Salt Lake City, UT, May 2012.
	Luis Guerra e Silva and L. Miguel Silveira, "Handling Intra-Die Variations in PSTA". In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 403-406, Lausanne, Switzerland, May 2011.
	Luis Guerra e Silva, Joel R. Phillips and L. Miguel Silveira, "Speedpath Analysis Under Parametric Timing Models". In Proceedings of the IEEE/ACM Design Automation Conference (DAC), pp. 268-273, Anaheim, CA, June 2010.
	Luis Guerra e Silva, Joel R. Phillips and L. Miguel Silveira, "Effective Corner-Based Techniques for Variation-Aware IC Timing Verification". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 1, January 2010.
	Luis Guerra e Silva, Zhenhai Zhu, Joel R. Phillips and L. Miguel Silveira, "Library Compatible Variational Delay Computation". In IFIP International Federation for Information Processing, Volume 249, VLSI-SoC: Research Trends in VLSI and Systems on Chip, G. De Micheli, S. Mir and R. Reis, Editors, pp 157-176, Springer, January 2008.
	Luis Guerra e Silva, Joel Phillips and L. Miguel Silveira, "Efficient Computation of the Worst-Delay Corner". In Proceedings of the IEEE/ACM Design, Automation and Test in Europe Conference (DATE), Nice, France, April 2007.
	Luis Guerra e Silva, Joel Phillips and L. Miguel Silveira, "Efficient Computation of the Exact Worst-Delay Corner". In IEEE/ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Austin, TX, February 2007.
	Luis Guerra e Silva, Zhenhai Zhu, Joel Phillips and L. Miguel Silveira, "Variation-Aware, Library Compatible Delay Modeling Strategy". In Proceedings of the Fourteenth International Conference on Very Large Scale Integration (VLSI-SoC 2006), Nice, France, October 2006. Best paper award.
	Luis Guerra e Silva, Afshin Abdollahi, Philip Chong, Christoph Albrecht, Joel Phillips and Andreas Kuehlmann, "OpenAccess Gear Timing". Invited talk at the 8th OpenAccess+ Conference, Santa Clara, California, April 2006.
	João Marques-Silva and Luis Guerra e Silva, "Solving Satisfiability in Combinational Circuits", in IEEE Design and Test of Computers, pp. 16-21, July-August 2003.
	C. Visweswariah, A. R. Conn and L. G. Silva, "Exploiting Optimality Conditions in Accurate Static Circuit Tuning", G. Di Pillo and A. Murli, Editors, High Performance Algorithms and Software for Nonlinear Optimization, Kluwer Academic Publishers, Dordrect, The Netherlands, pp. 356-374, 2003.
	Luis Guerra e Silva, João Marques-Silva, L. Miguel Silveira and Karem A. Sakallah, "Satisfiability Models and Algorithms for Circuit Delay Computation", in ACM Transactions on Design Automation of Electronic Systems, Vol. 7, No. 1, pp. 137-158, January 2002.
	João P. Marques-Silva and Luis Guerra e Silva, "Algorithms for Satisfiability in Combinational Circuits Based on Backtrack Search and Recursive Learning", in Proceedings of the XII Symposium on Integrated Circuits and Systems Design (SBCCI), Natal, Brasil, September/October 1999
	Luis Guerra e Silva, "Models and Algorithms for Timing Analysis of Combinational Circuits", Master Thesis, Instituto Superior Técnico, Lisboa, Portugal, June 1999.
	João P. Marques-Silva and Luis Guerra e Silva, "Algorithms for Satisfiability in Combinational Circuits Based on Backtrack Search and Recursive Learning", in IEEE/ACM International Workshop on Logic Synthesis (IWLS), Lake Tahoe, California, June 1999.
	Luis Guerra e Silva, João Marques-Silva and L. Miguel Silveira, "Algorithms for Solving Boolean Satisfiability in Combinational Circuits", in Proceedings of the IEEE/ACM Design, Automation and Test in Europe Conference (DATE), Munich, Germany, March 1999.
	Luis Guerra e Silva, João Marques-Silva, L. Miguel Silveira and Karem A. Sakallah, "Timing Analysis Using Propositional Satisfiability", in Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS), Lisboa, Portugal, September 1998.
	Luis Guerra e Silva, João Marques-Silva, L. Miguel Silveira and Karem A. Sakallah, "Realistic Delay Modeling in Satisfiability-Based Timing Analysis", in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, California, May 1998.
	Luis Guerra e Silva, João Marques-Silva, L. Miguel Silveira and Karem A. Sakallah, "Satisfiability Models and Algorithms for Circuit Delay Computation", in Proceedings of the ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Austin, Texas, December 1997.