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[1] Alexandre M. Amory, Cristiano Lazzari, Marcelo S. Lubaszewski, Fernando G. Moraes, A new test scheduling algorithm based on networks-on-chip as test access mechanisms, Journal of Parallel and Distributed Computing, In Press, Accepted Manuscript, Available online 10 October 2010, ISSN 0743-7315, DOI: 10.1016/j.jpdc.2010.09.008

[2] Cristiano Lazzari, Jorge Fernandes, Paulo Flores and José Monteiro. An Efficient Low Power Multiple-value Look-up Table targeting Quaternary FPGAs. Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation. Grenoble, France. LNCS 6448, pp. 84–93, 2010.

[3] Marcus Ritt, Carlos Arthur Lang Lisboa, Luigi Carro and Cristiano Lazzari. A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs Proceedings of the International Conference on Field Programmable Logic and Applications. Milan, Italy. Sep 2010. pp. 332-335. ISBN 978-0-7695-4179-2/10. DOI http://dx.doi.org/10.1109/FPL.2010.72

[4] Cristiano Lazzari and Paulo Flores and J. Monteiro and Luigi Carro, Voltage-mode Quaternary FPGAs: An Evaluation of Interconnections, IEEE International Symposium on Circuits and Systems (ISCAS 2010). Paris, France. May 2010. pp 869-872. ISBN 978-1-4244-5309-2.

[5] Cristiano Lazzari and Paulo Flores and Jose Carlos Monteiro and Luigi carro. A New Quaternary FPGA Based on a Voltage-mode Multi-valued Circuits, Proceedings of the Design, Automation & Test in Europe (DATE 2010). Dresden, Germany. Mar 2010, pp. 1797 - 1802, ISBN 978-1-4244-7054-9.

[6] Cristiano Lazzari and Adriel Ziesemer and Ricardo Reis. An Automated Design Methodology for Layout Generation targeting Power Leakage Minimization. In: 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009. Dec 2009, pp. 81-84. ISBN978-1-4244-5090-9. DOI http://dx.doi.org/10.1109/ICECS.2009.5410924..

[7] Cristiano Lazzari and Paulo Flores and Jose Carlos Monteiro. Power and Delay Comparison of Binary and Quaternary Arithmetic Circuits. IEEE International Conference on Signals, Circuits and Systems (SCS'09), Nov, 2009. ISBN 978-1-4244-4397-0. DOI http://dx.doi.org/10.1109/ICSCS.2009.5412586..

[8] Ricardo da Silva and Cristiano Lazzari and Henri Boudinov and Luigi Carro, CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs , Microelectronics Journal, 40(10), pp. 1466-1470 , Oct. 2009, Elsevier. DOI http://dx.doi.org/10.1016/j.mejo.2009.07.001..

[9] LAZZARI, C. ; REIS, R. .A Timing Closure Design Flow Using a Transistor level Automatic Layout Generator. In: Advanced Topics on VLSI Design. 1 ed. Porto Alegre: ufrgs, 2009, v. 2, p. 157-183.

[10] LAZZARI, C. ; ASSIS, T. ; KASTENSMIDT, F. ; WIRTH, G. ; ANGHEL, L. ; REIS, R. . An Analysis and Design Technique to Reduce SET Sensitivity in Combinational Integrated Circuits. In: 16th IFIP/IEEE International Conference on VLSI-Soc, 2008, Rhodes Island, Greece. VLSI-Soc, 2008. pp. 114-117.

[11] LAZZARI, C. ; ASSIS, T. ; KASTENSMIDT, F. ; WIRTH, G. ; ANGHEL, L. ; REIS, R. . SET-Factor: An Analysis and Design Tool to Reduce SET Sensitivity in Integrated Circuits. In: 13th IEEE European Test Symposium, 2008, Verbania, Italy. ETS08, 2008.

[12] LAZZARI, C. ; ASSIS, T. ; KASTENSMIDT, F. ; WIRTH, G. ; ANGHEL, L. ; REIS, R. . Asymmetric and Symmetric Transistor Sizing to Reduce SET Sensitivity in Integrated Circuits. In: 23th South Symposium on Microelectronics, 2008, Bento Gonçalves. 23th South Symposium on Microelectronics, 2008. p. 73-76.

[13] LAZZARI, C. ; ANGHEL, L. ; REIS, R. . A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis. Journal of Electronic Testing, v. 26, p. 625-633, 2007.

[14] ZIESEMER JUNIOR, Adriel Mota ; LAZZARI, Cristiano ; REIS, Ricardo . An educational tool for design automation of CMOS cells. In: MSE, 2007, San Diego. IEEE International Conference on Microelectronic Systems Education (2007 : San Diego, Estados Unidos). Proceedings, 2007.

[15] LAZZARI, C. ; ANGHEL, L. ; REIS, R. . A Transistor Placement Technique Using Genetic Algorithm And Analytical Programming. VLSI-SOC: From Systems to Silicon. : , 2007, v. 240, p. 331-344.

[16] LAZZARI, C. ; SANTOS, C. L. ; ZIESEMER JUNIOR, A. ; ANGHEL, L. ; REIS, R. . Efficient Timing Closure with a Transistor Level Design Flow. In: IFIP Conference on Very Large Scale Integration System-on-Chip, 2007, Atlanta. IFIP VLSI-SoC 2007, 2007.

[17] ZIESEMER JUNIOR, A. ; LAZZARI, C. ; REIS, R. . Transistor Level Automatic Layout Generator for non-Complementary CMOS Cells. In: IFIP Conference on Very Large Scale Integration System-on-Chip, 2007, Atlanta. IFIP VLSI-SoC 2007, 2007.

[18] LAZZARI, C. ; ASSIS, T. ; KASTENSMIDT, F. ; WIRTH, G. ; ANGHEL, L. ; REIS, R. . Efficient Transistor Sizing for Soft Error Protection in Combinational Logic Circuits. In: International Workshop on Dependable Circuit Design, 2007, Buenos Aires. DECIDE 2007, 2007.

[19] AMMARI, A.; ANGHEL, L.; LEVEUGLE, R.; LAZZARI, C.; REIS, R. SET Fault Injection Methods in Analog Circuits: Case Study. In: 8th IEEE Latin-American Test Workshop, 2007. Cuzco, Lima. 2007.

[20] ZIESEMER JUNIOR, Adriel Mota ; LAZZARI, Cristiano ; REIS, Ricardo . Automatic Transistor-Level Layout Generator of CMOS Cells. In: XXII SIM, 2007, Porto Alegre. South Symposium on Microelectronics (22. : 2007 : Porto Alegre, RS). Proceedings, 2007.

[21] LAZZARI, C. ; SANTOS, C. L. ; REIS, R. . A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits. In: 13th IEEE International Conference on Electronics, Circuits and Systems, 2006, Nice. 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. p. 660-663.

[22] LAZZARI, C. ; DOMINGUES, C. V. ; GUNTZEL, J. ; REIS, R. . A Novel Full Automatic Layout Generation Strategy For Statis CMOS Circuits. In: Manfred Glesner et al. (Org.). VLSI-SOC: Systems to Chips. New York, USA: Springer, 2006, p. 197-212.

[23] ANGHEL, L. ; LAZZARI, C. ; NICOLAIDIS, M. . Multiple Defects Tolerant Devices for for Unreliable Future Nanotechnologies. In: 7th IEEE Latin-American Test Workshop, 2006, Buenos Aires. 7th IEEE Latin-American Test Workshop, 2006. p. 186-191.

[24] LAZZARI, C. ; ANGHEL, L. ; REIS, R. . Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study. In: 12th IEEE International On-line Testing Symposium, 2006, Como. Italy. p. 165-170.

[25] LAZZARI, C. ; ANGHEL, L. ; REIS, R. . A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming. In: IFIP WG.5 Conference on Very Large Scale Integration System-on-Chip (VLSI-SoC 2005). Pert, Western Australia. pp 559-564. ISBN 07298-0610-3. 2005.

[26] SANTOS, C. L. ; FERRAO, D. ; LAZZARI, C. ; WILKE, G. ; GUNTZEL, J. ; REIS, R. . Effects of using a pin-to-pin delay model on a library-free transistor/gate sizing scheme. In: 48th Midwest Symposium on Circuits and Systems, 2005, Cincinnati, Ohio. 48th Midwest Symposium on Circuits and Systems, 2005. p. 315-318.

[27] LAZZARI, C. ; ANGHEL, L. ; REIS, R. . On Implementing a Soft Error Hardening Technique By Using an Automatic Layout Generator: Case Study. In: 11th IEEE International On-Line Testing Symposium, Saint Raphael, France. pp 29-34. ISBN 07695-2406-0. 2005.

[28] LAZZARI, C. ; ANGHEL, L. ; REIS, R. . Soft Error Circuit Hardening Techniques Implementation Using an Automatic Layout Generator. In: 6th IEEE Latin-American Test Workshop, 2005, Salvador. 6th IEEE Latin-American Test Workshop, 2005. p. 175-180.

[29] LAZZARI, C. . Automatic Full-Custom Layout Generation of Static CMOS Circuits Targeting Delay and Power Reduction. In: IFIP World Computer Congress, 2004, Toulouse. IFIP WCC Student Forum, 2004. pp 177-186.

[30] BASTIAN, F.; LAZZARI, C.; GUNTZEL, J.; REIS, R. A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool. PATMOS 2004. Santorini, Greece, pp 732-741. 2004.

[31] Lazzari, Cristiano; Domingues, Cristiano; Guntzel, Jose; Reis, Ricardo. A New Macro-cell Generation Strategy for three metal layer CMOS Technologies. VLSI-Soc'03. Darmstadt, Germany. pp 193-197. 2003.

[32] Santos, Cristiano; Wilke, Gustavo; Lazzari, Cristiano; Guntzel, Jose; Reis, Ricardo. A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. SBCCI'03. Sao Paulo-SP.Brazil. 2003.

[33] Lazzari, Cristiano; Guntzel, Jose; Reis, Ricardo.Timing-driven Automatic Layout Generation of Digital CMOS Circuits. SIM2003. Novo Hamburgo-RS. Brazil 2003

[34] Domingues, Cristiano; Lazzari, Cristiano; Reis, Ricardo. A CAD tool for IC layout in SOI technology. SIM2003. Novo Hamburgo-RS. Brazil. 2003

[35] Santos, Cristiano; Wilke, Gustavo; Lazzari, Cristiano; Guntzel, Jose; Reis, Ricardo. A Transistor Sizing Method Applied to an Automatic Layout Generator. SIM2003. Novo Hamburgo-RS. Brazil. 2003.

[36] Lazzari, Cristiano; et al. Designing a Fault Tolerant AES-Rijndael IP Core. LATW2003.Natal/RN. Brazil.2003.

[37] Hentschke, Renato; Lazzari, Cristiano; Guntzel, Jose; Reis, Ricardo; Lemon Dragon Physical Synthesis. SIM2002. Gramado/RS. Brazil. 2002.

[38] Panato, Alex; Neuberger, Gustavo; Lima, Fernanda; Lazzari, Cristiano; Reis, Ricardo; Testing and Protecting a Rijndael VHDL Description to Single Event Upsets SIM2002. Gramado/RS. Brazil. 2002.

[39] Lazzari, Cristiano; et al. Um IP de criptografia padrao Rijndael. IBERCHIP/2002. Guadalajara. Mexico. 2002.

[40] Lazzari, Cristiano; Cota, Erika; Carro, Luigi; Susin, Altamiro; Lubaszewski, Marcelo. Geracao Automatica de wrappers Compativeis com o Padrao P15000. IBERCHIP/2002. Guadalajara. Mexico. 2002.

[41] Lazzari, Cristiano; Adario, Alexandro M. S. VisualScalar: Uma Interface Grafica para a Ferramenta de Simulacao SimpleScalar. In: V SEMINARIO DE INTEGRACAO DA PESQUISA E POS GRADUACAO DA URI, 2001. Erechim. 2001.

[42] Lazzari, Cristiano; Adario, Alexandro M. S. VisualScalar: A Graphical Interface to the SimpleScalar Tool Simulators. In: 16 Microeletronics Seminar (SIM2001). Santa Maria/RS. 2001.

[43] Lazzari, Cristiano; Adario, Alexandro M. S. VisualScalar: Uma Interface Grafica para a Ferramenta de Simulacao SimpleScalar. In: VI SEMINARIO DE INICIACAO CIENTIFICA DA URI, 2000. Frederico Westphalen. 2000.

 

 
 
 
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