Publications by José Monteiro (as of October 2015)
Thesis
[A.2] J. Monteiro, A Computer-Aided Design Methodology for Low Power Sequential Logic Circuits,
PhD
Thesis, Massachusetts Institute of Technology, May 1996.
[A.1] J. Monteiro, Codificação de Máquinas de Estados em Síntese Automática de Circuitos Lógicos,
MSc
Thesis, Instituto Superior Técnico, August 1992.
Books
[B.9] J. Monteiro, R. van Leuken (editores) Integrated Circuit and System Design: Power and
Timing Modeling, Optimization and Simulation, Springer, February 2010.
[B.3] L. Svensson, J. Monteiro (editores) Integrated Circuit and System Design: Power and Timing
Modeling, Optimization and Simulation, Springer, February 2009.
[B.2] G. Arroz, J. Monteiro, A. Oliveira, Arquitectura de Computadores: dos Sistemas Digitais
aos Microprocessadores, IST Press, February 2007. (2nd Edition, July 2009; 3rd Edition, December 2014)
[B.1] J. Monteiro, S. Devadas, Computer-Aided Design Techniques for Low Power Sequential
Logic Circuits, Kluwer Academic Publishers, November 1996.
Book Chapters
[B.11] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Multiplierless Design of Linear DSP Transforms,
chapter in VLSI-SoC: The Advanced Research for Systems on Chip, editores S. Mir, C.-Y.
Tsui, R. Reis, O. Choy, Springer, August 2012.
[B.10] A. Gusmão, L. Silveira, J. Monteiro, Power Macro-Modeling using an Iterative LS-SVM
Method, chapter in VLSI-SoC: Technologies for Systems Integration, editores J. Becker,
M. Johann, R. Reis, Springer, June 2011.
[B.8] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Optimization Algorithms for Multiple Constant
Multiplications, chapter in Advanced Topics in VLSI Design II, editor R. Reis, UFGRS, pp
71-99, January 2009.
[B.7] R. Rodrigues, J. Monteiro, Review of the Algorithm Selection, chapter in Computational
Intelligence: Methods and Applications, editores Leszek Rutkowski et al., Exit Publishers,
September 2008.
[B.6] L. Oliveira, E. Costa, J. Monteiro, J. Martins, S. Bampi, C. Santos, D. Ferrão, R. Reis,
A Comparison of Layout Implementations of Pipelined And Non-Pipelined Signed Radix-4
Array Multiplier And Modified Booth Multiplier Architectures, chapter in VLSI-SoC: From
Systems to Silicon, editores R. Reis, A. Osseiran, H.-J. Pfleiderer, Springer, September
2007.
[B.5] E. Costa, J. Monteiro, S. Bampi, Gray Encoded Arithmetic Operators Applied to FFT and
FIR Dedicated Datapaths, chapter in VLSI-SOC: From Systems to Chips, editores M. Glesner,
R. Reis, L. Indrusiak, V. Mooney, H. Eveking, Springer, May 2006.
[B.4] J. Monteiro, R. Patel, V. Tiwari, Power Analysis and Optimization from Circuit to Register-
Transfer Levels, chapter in EDA for IC Implementation, Circuit Design And Process Tech-
nology, editores G. Martin, L. Lavagno, L. Scheffer, CRC Press, March 2006.
International Journals
[C.26] L. Aksoy, P. Flores, J. Monteiro, A Novel Method for the Approximation of Multiplierless
Constant Matrix Vector Multiplication, EURASIP Journal on Embedded Systems, Springer,
2016(1), pp. 1-11, May 2016.
[C.25] N. Lopes, J. Monteiro, Automatic Equivalence Checking of Programs With Uninterpreted
Functions and Integer Arithmetic, International Journal on Software Tools for Technology
Transfer (STTT), Springer, February 2015.
[C.24] D. Brito, T. Rabuske, J. Fernandes, P. Flores, J. Monteiro, Quaternary Logic Lookup Table
in Standard CMOS, IEEE Transactions on Very Large Scale Integration Systems (TVLSI),
23(2), pp. 306-316, February 2015.
[C.23] L. Aksoy, P. Flores, J. Monteiro, Exact and Approximate Algorithms for the Filter Design
Optimization Problem, IEEE Transactions on Signal Processing (TSP), 63(1), pp. 142-
154, January 2015.
[C.22] L. Aksoy, P. Flores, J. Monteiro, Multiplierless Design of Folded DSP Blocks, ACM Transac-
tions on Design Automation of Electronic Systems (TODAES), 20(1), pp. 14:1-14:24,
November 2014.
[C.21] L. Aksoy, P. Flores, J. Monteiro, A Tutorial on Multiplierless Design of FIR Filters: Al-
gorithms and Architectures, Circuits, Systems and Signal Processing, 33(6), pp. 1689-
1719, June 2014.
[C.20] J. Bispo, J. Cardoso, J. Monteiro, Hardware Pipelining of Repetitive Patterns in Processor
Instruction Traces, Journal of Integrated Circuits and Systems, 8(1), pp. 22-31, March
2013.
[C.19] J. Costa, J. Monteiro, Coverage-Directed Observability-Based Validation for Embedded
Software, ACM Transactions on Design Automation of Electronic Systems (TODAES),
18(2), pp. 19:1-19:20, March 2013.
[C.18] L. Aksoy, C. Lazzari, E. Costa, P. Flores, J. Monteiro, Design of Digit-Serial FIR Filters:
Algorithms, Architectures, and a CAD Tool, IEEE Transactions on Very Large Scale Integra-
tion Systems (TVLSI), 21(3), pp. 498-511, March 2013.
[C.17] C. Sampaio, J. Monteiro, L. Silveira, Analysis of the Conditions for the Worst Case Switching
Activity in Integrated Circuits, Analog Integrated Circuits and Signal Processing, 70(2), pp.
229-240, Springer, February 2012.
[C.16] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Optimization Algorithms for the Multiplierless
Realization of Linear Transforms, ACM Transactions on Design Automation of Electronic
Systems (TODAES), 17(1), pp. 3:1-3:27, Janeiro de 2012.
[C.15] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Finding the Optimal Tradeoff Between Area
and Delay in Multiple Constant Multiplications, Elsevier Journal on Microprocessors and
Microsystems: Embedded Hardware Design (MICPRO), 35(8), pp. 729-741, November
2011.
[C.14] C. Lazzari, J. Fernandes, P. Flores, J. Monteiro, Low Power Multiple-Value Voltage-Mode
Look-Up Table for Quaternary Field Programmable Gate Arrays, Journal of Low Power
Electronics (JOLPE), vol. 7, issue 2, pp 294-301, American Scientific Publishers,
April 2011.
[C.13] L. Pieper, E. Costa, S. Bampi, J. Monteiro, Efficient Dedicated Multiplication Blocks for 2's
Complement Radix-2n Array Multipliers, Journal of Computers, vol. 5, issue
10, pp 1502-1509, Academy Publisher, October 2010.
[C.11] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Exact and Approximate Algorithms for the
Optimization of Area and Delay in Multiple Constant Multiplications, IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, issue 27,
pp 1013-1026, June 2008.
[C.10] E. Costa, J. Monteiro, S. Bampi, A New Array Architecture for Signed Multiplication using
Gray Encoded Radix-2m Operands, Integration: the VLSI Journal, Elsevier Science Pu-
blishers, vol. 40, issue 2, pp 118-132, February 2007.
[C.9] J. Costa, L. Silveira, S. Devadas, J. Monteiro, Power Estimation using Probability
Polynomials, Design Automation for Embedded Systems, Springer, vol. 9, no. 1, pp 19-52,
March 2004.
[C.8] J. Monteiro, A. Oliveira, Implicit FSM Decomposition Applied to Low Power Design, IEEE
Transactions on VLSI Systems (TVLSI), 10(5) pp 560-565, October 2002.
[C.7] J. Monteiro, S. Devadas, A. Ghosh, Sequential Logic Optimization for Low Power Using
Input-Disabling Precomputation Architectures, IEEE Transactions on Computer-Aided De-
sign of Integrated Circuits and Systems (TCAD), 17(3) pp 279-284, March 1998.
[C.6] J. Monteiro, S. Devadas, Power Estimation Under User-Specified Input Sequences and
Programs, Integrated Computer-Aided Engineering, 5(2), pp 177-185, October 1998.
[C.5] J. Monteiro, S. Devadas, A. Ghosh, K. Keutzer, J. White, Estimation of Average Switching
Activity in Combinational Logic Circuits Using Symbolic Simulation, IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems (TCAD), 16(1) pp 121-127,
Janeiro de 1997.
[C.4] J. Monteiro, S. Devadas, Techniques for Power Estimation and Optimization at the Logic
Level: A Survey, Journal of VLSI Signal Processing Systems, 13(2/3) pp 259-276,
Agosto/September 1996.
[C.3] J. Monteiro, S. Devadas, A. Ghosh, Retiming Sequential Circuits for Low Power,
International Journal of High Speed Electronics and Systems, 7(2) pp 323-340, June 1996.
[C.2] C-Y. Tsui, J. Monteiro, M. Pedram, S. Devadas, A. Despain, B. Lin, Power Estimation
Methods for Sequential Logic Circuits, IEEE Transactions on VLSI Systems (TVLSI), 3(3)
pp 404-416, September 1995. Best paper award.
[C.1] M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, M. Papaefthymiou, Precomputation-Based
Sequential Logic Optimization for Low Power, IEEE Transactions on VLSI Systems (TVLSI),
2(4) pp 426-436, December 1994.
International Conferences
[D.93] L. Aksoy, P. Flores, J. Monteiro, A Novel Method for the Approximation of Multiplierless
Constant Matrix Vector Multiplication, 13th IEEE/IFIP International Conference on Embedded
and Ubiquitous Computing (EUC), October 2015. Best paper award.
[D.92] L. Aksoy, P. Flores, J. Monteiro, Approximation of Multiple Constant Multiplications Using
Minimum Look-Up Tables on FPGA, IEEE International Symposium on Circuits and Sys-
tems (ISCAS), Lisbon, Portugal, May 2015.
[D.91] L. Aksoy, P. Flores, J. Monteiro, Efficient Design of FIR Filters Using Hybrid Multiple
Constant Multiplications on FPGA, IEEE International Conference on Computer Design
(ICCD), Seul, South Korea, October 2014.
[D.90] L. Aksoy, P. Flores, J. Monteiro, ECHO: A Novel Method for the Multiplierless Design
of Constant Array Vector Multiplication, IEEE International Symposium on Circuits and
Systems (ISCAS), Melbourne, Australia, June 2014.
[D.89] L. Aksoy, P. Flores, J. Monteiro, Optimization of Design Complexity in Time-Multiplexed
Constant Multiplications, IEEE/ACM Design, Automation and Test in Europe (DATE),
Dresden, Germany, March 2014.
[D.88] N. Lopes, J. Monteiro, Weakest Precondition Synthesis for Compiler Optimizations, 15th In-
ternational Conference on Verification, Model Checking, and Abstract Interpretation (VM-
CAI), San Diego, CA, USA, January 2014.
[D.87] L. Aksoy, P. Flores, J. Monteiro, Towards the Least Complex Time-Multiplexed Constant
Multiplication, 21st IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC), Istanbul, Turkey, October 2013.
[D.86] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Exploration of Tradeoffs in the Design of Integer
Cosine Transforms for Image Compression, 21st European Conference on Circuit Theory
and Design (ECCTD), Dresden, Germany, September 2013.
[D.85] L. Pieper, E. Costa, J. Monteiro, Combination of Radix-2m Multiplier Blocks and Adder
Compressors for the Design of Efficient 2's Complement 64-bit Array Multipliers, 26th Sym-
posium on Integrated Circuits and System Design - SBCCI 2013, Curitiba, Brazil, September
2013.
[D.84] N. Lopes, J Monteiro, Automatic Equivalence Checking of UF+IA Programs, International
SPIN Symposium on Model Checking of Software - SPIN13, Stony Brook, NY, USA, June
2013. Best paper award.
[D.83] D. Brito, J. Fernandes, P. Flores, J. Monteiro, Standard CMOS Voltage-Mode QLUT Using
a Clock Boosting Technique, 11th IEEE International NEWCAS Conference, Paris, France,
June 2013.
[D.82] L. Aksoy, P. Flores, J. Monteiro, SIREN: A Depth-First Search Algorithm for the Filter
Design Optimization Problem, IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI),
Paris, France, May 2013.
[D.81] S. Ghissoni, E. Costa, J. Monteiro, R. Reis, Efficient Area and Power Multiplication Part
of FFT Based on Twiddle Factor Decomposition, 19th IEEE International Conference on
Electronics, Circuits and Systems – (ICECS), Seville, Spain, December 2012.
[D.80] D. Brito, J. Fernandes, P. Flores, J. Monteiro, Design and Characterization of a QLUT in a
Standard CMOS Process, IEEE International Conference on Electronics, Circuits and Sys-
tems (ICECS), Seville, Spain, December 2012.
[D.79] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Multiple Tunable Constant Multiplications:
Algorithms and Applications , IEEE/ACM International Conference on Computer-Aided Design
(ICCAD), San Jose, CA, USA, November 2012.
[D.78] J. Bispo, J. Cardoso, J. Monteiro, Hardware Pipelining of Runtime-Detected Loops, IEEE
XXV Symposium on Integrated Circuits and Systems Design (SBCCI), Brasília, Brazil, Sep-
tember 2012.
[D.77] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Design of Low-Complexity Digital Finite Impulse
Response Filters on FPGAs, Design Automation and Test in Europe (DATE), Dresden, Ger-
many, March 2012.
[D.76] S. Ghissoni, E. Costa, J. Monteiro, R. Reis, Combination of Constant Matrix Multiplication
and Gate-level Approaches for Area and Power Efficient Hybrid Radix-2 DIT FFT Reali-
zation, 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS),
Beirute, Líbano, December 2011.
[D.75] L. Aksoy, E. Costa, P. Flores, J. Monteiro, "A Hybrid Algorithm for the Optimization of
Area and Delay in Linear DSP Transforms", IEEE/IFIP 19th International Conference on
VLSI and System-on-Chip (VLSI-SoC), Hong-Kong, October 2011.
[D.74] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Optimization of Gate-level Area in High
Throughput Multiple Constant Multiplications, 20th European Conference on Circuit Theory
and Design (ECCTD), Linkoping, Suécia, August 2011.
[D.73] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Design of Low-Power Multiple Constant
Multiplications Using Low-Complexity Minimum Depth Operations, Great Lakes Symposium on
VLSI (GLSVLSI), Lausanne, Suíça, May 2011.
[D.72] L. Aksoy, C. Lazzari, E. Costa, P. Flores, J. Monteiro, Efficient Shift-Adds Design of Digit-
Serial Multiple Constant Multiplications, Great Lakes Symposium on VLSI (GLSVLSI),
Lausanne, Suíça, May 2011.
[D.71] L. Aksoy, C. Lazzari, E. Costa, P. Flores, J. Monteiro, Optimization of Area in Digit-serial
Multiple Constant Multiplications at Gate-level, IEEE International Symposium on Circuits
and Systems (ISCAS), Rio de Janeiro, Brasil, May 2011.
[D.70] L. Oliveira, G. Dessbesell, J. Martins, J. Monteiro, Hardware Implementation of a Centroid-
based Localization Algorithm for Mobile Sensor Networks, IEEE International Symposium
on Circuits and Systems (ISCAS), Rio de Janeiro, Brasil, May 2011.
[D.69] S. Ghissoni, E. Costa, C. Lazzari, J. Monteiro, L. Aksoy, R. Reis, Radix-2 Decimation in
Time (DIT) Implementation Based on a Matrix-Multiple Constant Multiplication Approach,
17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Atenas,
Grécia, December 2010.
[D.68] L. Oliveira, G. Dessbesell, J. Martins, J. Monteiro, CentroidM: a Centroid-based Localiza-
tion Algorithm for Mobile Sensor Networks, IEEE XXIII Symposium on Integrated Circuits
and Systems Design (SBCCI), São Paulo, Brasil, September 2010.
[D.67] C. Lazzari, J. Fernandes, P. Flores, J. Monteiro, An Efficient Low Power Multiple-value
Look-up Table Targeting Quaternary FPGAs, International Workshop on Power and Timing
Modeling, Optimization and Simulation (PATMOS), Grenoble, França, September 2010.
[D.66] D. Jaccottet, E. Costa, L. Aksoy, P. Flores, J. Monteiro, Design of Low-Complexity and
High-Speed Digital Finite Impulse Response Filters, International Conference on VLSI and
System on Chip (VLSI-SoC), pp. 292-297, Madrid, Espanha, September 2010.
[D.65] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Optimization of Area and Delay at Gate-Level in
Multiple Constant Multiplications, Euromicro Conference on Digital System Design (DSD),
pp. 3-10, Lile, França, August 2010.
[D.64] C. Lazzari, P. Flores, J. Monteiro, L. Carro, Voltage-mode Quaternary FPGAs: An Evalu-
ation of Interconnections, IEEE International Symposium on Circuits and Systems (ISCAS
2010), pp. 869-872, Paris, França, May 2010.
[D.63] C. Lazzari, P. Flores, J. Monteiro, L. Carro, A New Quaternary FPGA Based on a Voltage-
mode Multi-valued Circuit, IEEE/ACM Design, Automation and Test in Europe (DATE),
Dresden, Germany, pp. 1797-1802, March 2010.
[D.62] C. Sampaio, J. Monteiro, L. Silveira, Analysis of the Conditions for Worst Case Switching
Activity in Integrated Circuits, IEEE Latin America Symposium on Circuits and Systems
(LASCAS), Iguaçu, Brasil, February 2010.
[D.61] C. Lazzari, P. Flores, J. Monteiro, Power and Delay Comparison of Binary and Quaternary
Arithmetic Circuits, International Conference on Signals, Circuits and Systems (SCS’09),
Jerba, Tunísia, November 2009.
[D.60] A. Gusmão, L. Silveira, J. Monteiro, Power Macro-Modeling using an Iterative LS-SVM
Method, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC),
Florianopolis, Brasil, October 2009.
[D.59] J. Costa, J. Monteiro, Observability-based Coverage-directed Path Search using PBO for
Automatic Test Vector Generation, IFIP/IEEE International Conference on Very Large Scale
Integration (VLSI-SoC), Florianopolis, Brasil, October 2009.
[D.58] S. Ghissoni, J. Martins, R. Reis, J. Monteiro, Analysis of Power Consumption Using a
New Methodology for the Capacitance Modeling of Complex Logic Gates, International
Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Delft,
Holanda, September 2009.
[D.57] J. Costa, J. Monteiro, A MILP-based Approach to Path Sensitization of Embedded Software,
IEEE/ACM Design, Automation and Test in Europe (DATE), Nice, França, April 2009.
[D.56] A. Gusmão, L. Silveira, J. Monteiro, Parameter Tuning in SVM-Based Power Macro-
Modeling, IEEE International Symposium on Quality Electronic Design (ISQED), San Jose,
California, USA, March 2009.
[D.55] L. Pieper, E. Costa, S. Bampi, J. Monteiro, Efficient Dedicated Multiplication Blocks for
2's Complement Radix-16 and Radix-256 Array Multipliers, International Conference on
Signals, Circuits & Systems (SCS08), Hammamet, Tunísia, November 2008.
[D.54] P. Morgado, P. Flores, J. Monteiro, L. Silveira, Generating Worst-Case Stimuli for Accurate
Power Grid Analysis, International Workshop on Power and Timing Modeling, Optimization
and Simulation (PATMOS), Lisboa, Portugal, September 2008.
[D.53] J. Costa, J. Monteiro, Computation of the Minimal Set of Paths for Observability-Based
Statement Coverage, 15th International Conference Mixed Design of Integrated Circuits and
Systems (MIXDES), Poznan, Polónia, June 2008.
[D.52] L. Pieper, E. Costa, S. Almeida, S. Bampi, J. Monteiro, Efficient Dedicated Structures for the
Radix-16 Multiplication, IBERCHIP XIV Workshop, Puebla, México, February 2008.
[D.51] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Effect of Number Representation on the Achieva-
ble Minimum Number of Operations, IEEE Workshop on Signal Processing Systems (SiPS),
Xangai, China, pp 424-429, October 2007.
[D.50] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Minimum Number of Operations under a General
Number Representation for Digital Filter Synthesis, IEEE European Conference on Circuit
Theory and Design (ECCTD), Sevilha, Espanha, August 2007.
[D.49] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Area Optimization of Digital FIR Filters using
Gate-Level Metrics, IEEE/ACM Design Automation Conference (DAC), San Diego, CA,
USA, pp 420-423, June 2007.
[D.48] R. Santos, J. Monteiro, Foot Fingerprints, IADIS International Conference on Applied Com-
puting, Salamanca, Espanha, February 2007.
[D.47] L. Aksoy, E. Costa, P. Flores, J. Monteiro, ASSUMEs: Heuristic Algorithms for Optimization
of Area and Delay in Digital Filter Synthesis, IEEE International Conference on Electronics,
Circuits and Systems (ICECS), Nice, França, December 2006.
[D.46] E. Costa, P. Flores, J. Monteiro, Exploiting General Coefficient Representation for the Op-
timal Sharing of Partial Products in MCMs, IEEE XIX Symposium on Integrated Circuits
and Systems Design (SBCCI), Ouro Preto, Brasil, September 2006.
[D.45] L. Aksoy, E. Costa, P. Flores, J. Monteiro, Optimization of Area Under a Delay Constraint in
Digital Filter Synthesis Using SAT-Based Integer Linear Programming, IEEE/ACM Design
Automation Conference (DAC), San Francisco, CA, USA, pp 669-674, July 2006.
[D.44] P. Flores, J. Monteiro, E. Costa, An Exact Algorithm for the Maximal Sharing of Par-
tial Terms in Multiple Constant Multiplications, IEEE/ACM International Conference on
Computer-Aided Design (ICCAD), San Jose, CA, USA, pp 13-16, November 2005.
[D.43] J. Monteiro, J. Fernandes, L. Silveira, A Case for a Triangular Waveform Clock Signal, IFIP
VLSI-SOC, pp 72-77, Perth, Austrália, October 2005.
[D.42] L. Oliveira, C. Santos, D. Ferrão, E. Costa, J. Monteiro, J. Martins, S. Bampi, R. Reis,
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-
4 Array Multiplier and Modified Booth Multiplier Architectures, IFIP VLSI-SOC, pp
78-82, Perth, Austrália, October 2005.
[D.41] M. Fonseca, E. Costa, S. Bampi, J. Monteiro, Design of a Radix-2n Hybrid Array Multiplier
Using Carry Save Adders, IEEE XVIII Symposium on Integrated Circuits and Systems Design
(SBCCI), pp 221-224, Florianópolis, Brasil, September 2005.
[D.40] E. Costa, P. Flores, J. Monteiro, Maximal Sharing of Partial Terms in MCM under Mini-
mal Signed Digit Representation, IEEE European Conference on Circuit Theory and Design
(ECCTD), Cork, Irlanda, September 2005.
[D.39] V. Rosa, S. Bampi, E. Costa, J. Monteiro, Performance Evaluation of Parallel FIR Filter
Optimizations in ASICs and FPGA, IEEE International Midwest Symposium on Circuits
and Systems (MWSCAS 2005), pp 1481-1484, Cincinnati, OH, USA, August 2005.
[D.38] M. Fonseca, E. Costa, S. Bampi, J. Monteiro, Performance Optimization of Radix-2n Multi-
pliers using Carry Save Adders, Iberchip, S. Salvador, Brasil, March 2005.
[D.37] V. Rosa, E. Costa, S. Bampi, J. Monteiro, An Improved Synthesis Method for Low Power
Hardwired FIR Filters, IEEE XVII Symposium on Integrated Circuits and Systems Design
(SBCCI), pp 237-241, Porto Galinhas, Brasil, September 2004.
[D.36] L. Oliveira, E. Costa, S. Bampi, J. Martins, J. Monteiro, Array Hybrid Multiplier versus
Modified Booth Multiplier: Comparing Area and Power Consumption of Layout Implemen-
tations of Signed Radix-4 Architectures, 2004 IEEE International Midwest Symposium on
Circuits and Systems (MWSCAS 2004), pp II-213 - II-216, Hiroshima, Japão, July 2004.
[D.35] E. Costa, S. Bampi, J. Monteiro, Low Power Architectures for FFT and FIR Dedicated
Datapaths, IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2003), pp
1514-1519, Cairo, Egipto, December 2003.
[D.34] E. Costa, S. Bampi, J. Monteiro, Gray Encoded Arithmetic Operators Applied to FFT and
FIR Dedicated Datapaths, IFIP VLSI-SOC, pp 307-312, Darmstadt, Germany,
Dezembro de 2003.
[D.33] E. Costa, S. Bampi, J. Monteiro, A New Pipelined Array Architecture for Signed Multiplica-
tion, IEEE XVI Symposium on Integrated Circuits and Systems Design (SBCCI), pp 65-70,
São Paulo, Brasil, September 2003.
[D.32] J. Portela, E. Costa, J. Monteiro, Optimal Combination of Number of Taps and Coeffici-
ent Bit-Width for Low Power FIR Filter Realization, IEEE European Conference on Circuit
Theory and Design (ECCTD), pp 145-148, Cracóvia, Polónia, September 2003.
[D.31] E. Costa, S. Bampi, J. Monteiro, A New Architecture for Signed Radix-2m Pure Array Multi-
pliers, IEEE International Conference on Computer Design (ICCD), pp 112-117, Frei-
burg, Germany, September 2002.
[D.30] E. Costa, S. Bampi, J. Monteiro, A New Architecture for 2's Complement Gray Encoded Ar-
ray Multiplier, IEEE XV Symposium on Integrated Circuits and Systems Design (SBCCI),
pp 14-19, Porto Alegre, RS, Brasil, September 2002.
[D.29] E. Costa, S. Bampi, J. Monteiro, FIR Filter Design using Low Power Arithmetic Operators,
IEEE 5th Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp 314-317,
Brno, República Checa, April 2002.
[D.28] E. Costa, S. Bampi, J. Monteiro, Power Efficient Arithmetic Operand Encoding, XIV Sympo-
sium on Integrated Circuits and Systems Design (SBCCI), Brasília, Brasil, pp 201-206,
September 2001.
[D.27] J. Portela, J. Monteiro, Power Optimized Viterbi Decoder Implementation Through Archi-
tectural Transforms, XIV Symposium on Integrated Circuits and Systems Design (SBCCI),
Brasília, Brasil, pp 212-217, September 2001.
[D.26] E. Costa, S. Bampi, J. Monteiro, Power Optimization using Coding Methods on Arithmetic
Operators, IEEE International Symposium on Signals, Circuits and Systems (SCS), pp 505-508,
Iasi, Roménia, July 2001.
[D.25] J. Costa, S. Devadas, J. Monteiro, Observability Analysis for Embedded Software in a
Coverage-Directed Validation Methodology, IEEE/ACM International Conference on
Computer-Aided Design (ICCAD), San Jose, CA, USA, pp 27-32, November 2000.
[D.24] J. Martins, R. Reis, J. Monteiro, Capacitance and Power Modeling at the Logic Level, Pro-
ceedings of the IFIP International Conference on Chip Design Automation, Beijing, China,
August 2000.
[D.23] A. Mota, N. Ferreira, A. Oliveira, J. Monteiro, Low Power ISDN Interface for Portable PCs,
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and
Design (ISLPED), Rapallo, Itália, July 2000.
[D.22] R. Ferreira, A-M. Trullemans, J. Costa, J. Monteiro, Probabilistic Bottom-up RTL Power Es-
timation, Proceedings of the IEEE/ACM International Symposium on Quality of Electronic
Design (ISQED), pp 439-446, San Jose, CA, USA, March 2000.
[D.21] J. Monteiro, A. Oliveira, FSM Decomposition by Direct Circuit Manipulation Applied to
Low Power Design, Proceedings of the IEEE/ACM Asia and South Pacific Design Au-
tomation Conference (ASPDAC), pp 351-358, Yokohama, Japão, Janeiro de 2000.
[D.20] A. Mota, N. Ferreira, A. Oliveira, J. Monteiro, Integrating Dynamic Power Management in
the Design Flow, Proceedings of the IFIP VLSI-SoC, pp 233-244, Lisboa, Portugal,
December 1999.
[D.19] A. Freitas, A. Oliveira, J. Monteiro, H. Neto, Exact Power Estimation Using Word Level
Transition Probabilities, Ninth International Workshop on Power and Timing Modeling,
Optimization and Simulation (PATMOS), pp 355-364, Kos, Grécia, October 1999.
[D.18] J. Monteiro, Power Optimization using Dynamic Power Management, XII Symposium on
Integrated Circuits and Systems Design (SBCCI), pp 134-139, Natal, RN, Brasil, Se-
tembro/October 1999.
[D.17] J. Costa, J. Monteiro, L. Silveira, S. Devadas, A Probabilistic Approach for RT-Level Power
Modeling, IEEE International Conference on Electronics, Circuits and Systems (ICECS),
pp 911-914, Paphos, Chipre, September 1999.
[D.16] J. Costa, L. Silveira, J. Monteiro, Sequential Power Estimation using Probability Polynomi-
als, IEEE International Symposium on Signals, Circuits and Systems (SCS), pp 17-20,
Iasi, Roménia, July 1999.
[D.15] P. Flores, J. Costa, H. Neto, J. Monteiro, J. Marques-Silva, Assignment and Reordering of
Incompletely Specified Patterns Targetting Minimum Power Dissipation, 12th IEEE Interna-
tional Conference on VLSI Design, pp 37-41, Goa, India, Janeiro de 1999.
[D.14] J. Monteiro, Techniques for Power Management at the Logic Level, IEEE International Con-
ference on Electronics, Circuits and Systems (ICECS), pp 2.181-2.184, Lisboa, Portugal,
September 1998.
[D.13] J. Monteiro, A. Oliveira, Finite State Machine Decomposition for Low Power, IEEE/ACM
35th Design Automation Conference (DAC), pp 758-763, San Francisco, CA, USA,
June 1998.
[D.12] A. Mota, J. Monteiro, A. Oliveira, Power Optimization of Combinational Modules Using
Self-Timed Precomputation, IEEE International Symposium on Circuits and Systems (ISCAS),
pp II.17-II-20, Monterey, CA, USA, May 1998.
[D.11] J. Costa, P. Flores, H. Neto, J. Monteiro, J. Marques-Silva, Exploiting Don't Cares in Test
Patterns to Reduce Power During BIST, IEEE European Test Workshop (ETW), Sitges,
Espanha, May 1998.
[D.10] J. Monteiro, J. Marques-Silva, Testability Analysis of Circuits using Data-Dependent Power
Management, IX IFIP International Conference on Very Large Scale Integration, pp 353-364,
Gramado, RS, Brasil, August 1997.
[D.9] J. Costa, J. Monteiro, S. Devadas, Switching Activity Estimation using Limited Depth Recon-
vergent Path Analysis, IEEE/ACM International Symposium on Low Power Electronics and
Design (ISLPED), pp 184-189, Monterey, CA, USA, August 1997.
[D.8] J. Marques-Silva, J. Monteiro, K. Sakallah, Test Pattern Generation for Circuits Using Power
Management Techniques, IEEE European Test Workshop (ETW), Cagliari, Itália, May 1997.
[D.7] J. Monteiro, S. Devadas, P. Ashar, A. Mauskar, Scheduling Techniques to Enable Power
Management, IEEE/ACM 33rd Design Automation Conference (DAC), pp 349-352,
Las Vegas, NV, USA, June 1996.
[D.6] J. Monteiro, S. Devadas, Techniques for the Power Estimation of Sequential Logic Circuits
Under User-Specified Input Sequences and Programs, IEEE/ACM International Symposium
on Low Power Electronics and Design (ISLPED), pp 33-38, Laguna Beach, CA, USA,
April 1995.
[D.5] J. Monteiro, J. Rinderknecht, S. Devadas, A. Ghosh, Optimization of Combinational and Se-
quential Logic Circuits for Low Power Using Precomputation, 1995 Chapel Hill Conference
on Advanced Research in VLSI, pp 430-444, Chapel Hill, NC, USA, March 1995.
[D.4] M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, M. Papaefthymiou, Precomputation-Based
Sequential Logic Optimization for Low Power, IEEE/ACM International Conference on
Computer-Aided Design (ICCAD), pp 74-81, San Jose, CA, USA, November 1994.
[D.3] J. Monteiro, S. Devadas, B. Lin, A Methodology for Efficient Estimation of Switching Acti-
vity in Sequential Logic Circuits, IEEE/ACM 31st Design Automation Conference (DAC),
pp 12-17, San Diego, CA, USA, June 1994.
[D.2] J. Monteiro, J. Kukula, S. Devadas, H. Neto, Bitwise Encoding of Finite State Machines,
IEEE 7th International Conference on VLSI Design, pp 379-382, Calcutta, India, Ja-
neiro de 1994.
[D.1] J. Monteiro, S. Devadas, A. Ghosh, Retiming Sequential Circuits for Low Power, IEEE/ACM
International Conference on Computer-Aided Design (ICCAD), pp 398-402, Santa
Clara, CA, USA, November 1993.