December 1-4, Lisbon, Portugal
Meridien Hotel
Hours | Wednesday, December 1st | Thursday, December 2nd | Friday, December 3rd | |||
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Room | Coimbra A | Coimbra B | Coimbra A | Coimbra B | Coimbra A | Coimbra B |
9:00-10:30 | Keynote Address Dr. Benny Madsen, National Semiconductor Corporation Plenary - Room Coimbra B |
4A Analog Systems Design |
4B Test and Verification |
8A Image Processing |
8B Analog CAD and Interconnect |
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10:30-11:00 | Coffee Break | Coffee Break | Coffee Break | |||
11:00-12:30 | 1 RF Design and Analysis Special Session Plenary - Room Coimbra B |
5A Analog Modeling and Design |
5B Verification and Simulation |
9A Interconnect Process Parametrization Embedded Tutorial |
9B Timing and Verification Special Session |
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12:30-14:00 | Lunch | Lunch | Lunch | |||
14:00-16:00 | 2A Low Power Design |
2B High-level Synthesis and Verification of Embedded Systems |
6 CAD for Microelectromechanical Systems Embedded Tutorial Plenary - Room Coimbra B |
10A Memory and Systems Design |
10B CAD for Physical Design |
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16:00-16:30 | Coffee Break | Coffee Break | Coffee Break | |||
16:30-18:00 | 3A Microsystems Special Session |
3B Architectural Synthesis and Verification Special Session |
7A Reconfigurable Hardware Systems Special Session |
7B Video Systems on Chip Embedded Tutorial |
11A Reconfigurable Computing |
11B Fundamental CAD Algorithms |
18:30-19:30 | Conference Reception | |||||
20:00-22:30 | Conference Banquet |
New Wireless Connectivity Standards:
Enabling "True" Information Mobility Dr. Benny MadsenTechnical Director, Wireless Communications National Semiconductor Corporation
Organizer: Jaijeet Roychowdury, Bell Labs, USA Chairs: Jaijeet Roychowdhury, Lucent Bell Labs, U.S.A. José Carlos Pedro, U. Aveiro, IT/Aveiro, Portugal
Integrated Circuit Techniques for Wireless Transceivers Mihai Banu Bell Labs Lucent Tech, NJ, USATrends in RF Simulation Algorithms Joel Phillips, Dan Feng Cadence Design Systems, San Jose, CA, U.S.A.
Device Modeling and Measurement for RF Systems Franz Sischka HP-EESof, CA, USA
Chairs: Wolfgang Nebel, Oldenburg Univ., Germany Mircea Stan, University of Virginia, U.S.A. Single Ended Pass-Transistor Logic - A comparison with CMOS and CPL Mihai Munteanu, Peter A. Ivey, Luke Seed, Marios Psilogeorgopoulos, Istvan Bogdan University of Sheffield, E.E.E. Department, Electronic Systems Group, Sheffield, U.K.Multithreshold Voltage Technology for Low Power Bus Architecture A. Rjoub, O. Koufopavlou VLSI Design Laboratory,, Department of Electrical and Computer Engineering, University of Patras, Patras, Greece
Integrating Dynamic Power Management in the Design Flow António Mota, Nuno Ferreira, Arlindo Oliveira, José Monteiro IST/INESC, Lisboa, Portugal
Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI Stefan Lachowicz +, Kamran Eshraghian +, Hans-Jörg Pfleiderer * + Edith Cowan University, Australia * University of Ulm, Germany
Chairs: Jochen Jess, Eindhoven U., The Netherlands Klaus Buchenrieder, Siemens, Germany Architectural Transformations for Hierarchical Algorithmic Descriptions Marcio Yukio Teruya, Marius Strum and Wang Jiang Chau Department of Electronic Enginnering, Escola Politecnica da Universidade de Sao Paulo, BrazilAn Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs João M P Cardoso +, Horácio C Neto * + University of Algarve/INESC, Portugal * IST/INESC, Lisboa, Portugal
Object-Oriented Modeling and Co-Simulation of Embedded Electronic Systems Flávio Rech Wagner +, Marcio Oyamada +, Luigi Carro *, Marcio Kreutz + + Federal Univ. of Rio Grande do Sul, Computer Science Institute, Department of Electrical Enginnering, Porto Alegre, Brazil * Universidade Federal do Rio Grande do Sul, Electrical Engineering Department, Porto Alegre, Brazil
Architectura Synthesis with Interconnection Cost Control Christophe Jégo, Emmanuel Casseau, Eric Martin LESTER Laboratory, UBS Univ., France
Organizers: Manfred Glesner, TU Darmstadt, Germany Klaus Mueller-Glaser, TU Karlsruhe, Germany Chairs: Manfred Glesner, Darmstad U., Germany
CAE environment for electromechanical microsystems R. Lerch, M. Kaltenbacher, H. Landes Institute of Electrical Measurement Technology, University of LinzCost Consideration for Application Specific Microsystems' Physical Design Stages - A new approach for Microtechnological Process Design R. Brueck, A. Priebe, K. Hahn Institut of Computer Structures, University of Siegen, Germany
Moving MEMS into Mainstream Applications: The MEMSCAP Solution K. Liateni, D. Moulinier, B. Affour, A. Delpoux, J.M. Karam MEMSCAP, France
Organizer: Srinivas Devadas, MIT, USA Chairs: Srinivas Devadas, MIT, USA
Hardware Synthesis from Term Rewriting Systems James C. Hoe and Arvind MIT Laboratory for Computer Science, MIT, Cambridge, MA, USAA Synthesis Algorithm for Modular Design of Pipelined Circuits Maria-Cristina Marinescu and Martin Rinard MIT Laboratory for Computer Science, MIT, Cambridge, MA, USA
Chairs: Przemyslaw Bakowski, IRESTE, France Wim Diels, IMEC, Belgium Optimizing Mixer Noise Performance: A 2.4 GHz Downconversion Gilbert Mixer for W-CDMA Application Shenggao Li, Yue Wu, Chunlei Shi, Mohammed Ismail Analog VLSI Lab, The Ohio-state University, OH, USAAn Analog Non-Volatile Storage System for Audio Signals with Signal Conditioning for Mobile Communication Devices Devices Geoffrey B. Jackson, Saleel V. Awsare, Lawrence D. Engh, Peter Holzmann, Oliver, C. Kao, Carl R. Palmer, Aditya Raina Information Storage Devices, a Winbond Company, CA, USA
A Design of Operational Amplifier for Sigma Delta Modulators using 0.35um CMOS Process Bingxin Li, Hannu Tenhunen Electronic System Design Laboratory, Royal Institute of Technology, Sweden
Chairs: Gustavo Alves, Porto Univ., Portugal Marcelo Lubaszewski, UFRGS, Brazil The clustering effect on defect-level modeling José T. de Sousa IST/INESC, Lisboa, PortugalFASTNR: an Efficient Fault Simulator for Linear and Nonlinear DC Circuits J. Soares Augusto and C. F. Beltran Almeida IST/INESC, Lisboa, Portugal
Design Error Diagnosis in Digital Circuits without Error Model Raimund Ubar +, Dominique Borrione * + Tallinn Technical University, Estonia * TIMA-UJF, Grenoble, France
Chairs: Rolf Becker, Phillips, The Netherlands Dinis Magalhães Santos, Aveiro Univ., Portugal A Low Power CMOS Micromixer for GHz Wireless Applications Yue WU +*, Shenggao Li +, Mohammed Ismail +*, H. Kan Olsson * + Analog VLSI Lab, The Ohio State University, OH, U.S.A. * Radio Electronics Laboratory, Royal Institute of Technology, SwedenNonlinearity Analysis of a Short Channel CMOS Circuit for RFIC Applications Yue WU +*, Hog-Sun Kim, +*, Fredrik Jonsson *, Mohammed Ismail +*, H. Kan Olsson * + Analog VLSI Lab, The Ohio State University, OH, U.S.A. * Radio Electronics Laboratory, Royal Institute of Technology, Sweden
A Fast Parametric Model for Contact-Substrate Coupling Nasser Masoumi, Mohamed I. Elmasry, Safeiddin Safavi-Naeini Department of Electrical and Computer Engineering, University of Waterloo, Canada
Chairs: Antonio Leal, IST/INESC, Portugal José T. de Sousa, IST/INESC, Portugal Verification of Abstracted Instruction Cache of TITAC2: A Case Study Tomohiro Yoneda Department of Computer Science, Tokyo Institute of Technology, JapanSpeeding Up Look-up-Table Driven Logic Simulation Rajeev Murgai +, Fumiyasu Hirose *, Masahiro Fujita + + Fujitsu Laboratories of America, CA, U.S.A. * Cadence Japan, Japan
(S) Efficient Verification of Behavioral Models using Sequential Sampling Technique Tom Chen +, Isabelle Munn *, Anneliese von Mayrhauser *, Amjad Hajjar + + Department of Electrical and Computer Engineering, Colorado State Univ., Colorado, U.S.A. * Department of Computer Science, Colorado State University, Colorado, U.S.A.
(S) Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies S. Raimbault, G. Sassatelli, G. Cambon, M. Robert, S. Pillement, L. Torres Laboratoire d'Informatique, de Robotique et de Microéléctronique de Montpellier, Université Montpellier II / CNRS, France
Chairs: Bernard Courtois, IMAG, France Karl-Heinz Diener, Fraunhofer Institute, Germany
A Methodology and Associated CAD Tools for Support of Concurrent Design of MEMS Bart F. Romanowicz, M. H. Zaman, Stephen F. Bart, V. L. Rabinovich, I. Tchertkov, C. Hsu, John R. Gilbert Microcosm Technologies, Cambridge, MA, USA
Organizer: Sergio Bampi, URFGS, Brazil Chairs: Sergio Bampi, UFRGS, Brazil Valery Sklyarov, U. Aveiro, INESC/Aveiro, Portugal
Reconfigurable Computing: Viable Applications and Trends Alexandro Adario, Sergio Bampi UFRGS University, BrasilILP-Based Board-Level Routing of Multi-Terminal Network Prototyping Reconfigurable Interconnect Andreas Kirschbaum, Juergen Becker, Manfred Glesner Technical Univ. Darmstadt, Germany
Chairs: Leonel Sousa, IST/INESC, Portugal Paulo Ferreira, Aveiro Univ., Portugal
An Interface Based Approach to the Design of Video Systems On Chip J.Y. Brunel and W. M. Kruijtzer Philips Research Labs, The Netherlands
Chairs: António Sousa-Pereira, Aveiro Univ., Portugal Leonel Sousa, IST/INESC, Portugal A Feature Associative Processor for Image Recognition based on A-D merged Architecture Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi and Takashi Morie Faculty of Electrical Engineering, Hiroshima University, JapanMassively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications A. M. Rassau +*, G. Alagoda +, D. Lucas +, J. Austin-Crowe +, K. Eshraghian + + Centre for Very High Speed Microelectronic Systems, Edith Cowan University, WA, Australia * Department of Cybernetics, University of Reading, Reading, U.K.
Implementation of a Wavelet Transform Architecture for Image Processing Camille Diou, Lionel Torres, Michel Robert LIRMM, Université Montpellier II, Montpellier, France
Chairs: Jose Huertas, Univ. Sevilla, Spain Mattan Kamon, Microcosm, U.S.A. Efficient RLC Macromodels for Digital IC Interconnect Bogdan Tutuianu +, Daksh Lehther +, Madhulima Pandey +, Ross Baldick * + Motorola Inc., Somerset Design Center, Austin TX, U.S.A * Department of Electrical and Computer Engineering, University of Texas at Austin, Austin TX U.S.A.A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications Alex Doboli, Ranga Vemuri Digital Design Environment Laboratory, Dept. of ECECS, University of Cincinnati, U.S.A.
(S) A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements Adrian Nunez-Aldana, Ranga Vemuri Electrical and Computer Engineering Department, University of Cincinnati, USA.
(S) RF interface design using mixed-mode methodology Augusto Gallegos +, Philippe Silvestre +, Michel Robert *, Daniel Auvergne * + VLSI Technology, Wireless Communication Research, Phillips Semiconductors, Sophia-Antipolis, France * Laboratoire LIRMM, CNRS, Universite de Montpellier II, Montpellier, France
Chairs: Mattan Kamon, Microcosm, U.S.A. Edoardo Charbon, Cadence Design Systems, U.S.A.
SIPPs, Why Do We Need a New Standard for Interconnect Process Parameters? Martin G. Walker, Keh-Jeng (KJ) Chang, Christophe J. Bianchi Frequency Technology, Santa Clara, CA, USA
Organizers: Marios Papaefthymiou, U. Michigan, Ann Arbor, MI, U.S.A. Karem Sakallah, U. Michigan, Ann Arbor, MI, U.S.A. Chairs: Karem Sakallah, Univ. Michigan, Ann Arbor, U.S.A.
Recent Advances in High-Speed Low-Power Asynchronous Circuits Peter Beerel University of Southern California, CA, USASolving Design Problems with Static Timing Analysis Tim Burks Magma Design Automation, CA, USA
Retiming Theory and Practice Marios Papaefthymiou University of Michigan, Ann Arbor, MI, USA
Chairs: Guilherme Arroz, IST, Portugal Arlindo Oliveira, IST/INESC, Portugal An IEEE Compliant Floating Point MAF R. V. K. Pillai +, D. Al-Khalili *, A. J. Al-Khalili + + Concordia University, Montreal, Canada * Royal Military College of Canada, Kingston, CanadaDesign and Analysis of On-Chip CPU Pipelined Caches C. Ninos, H. T. Vergos & D. Nikolos Computer Technology Institute, Dept. of Computer Engineering and Informatics, University of Patras, Greece
(S) Synchronous to Asynchronous conversion - A case study: the Blowfish algorithm implementation João M. S. Alcântara +, Sergio C. Salomão +*, Edson do Prado Granja +, Vladimir C. Alves +, Felipe M. G. Franca + + COPPE/Federal University of Rio de Janeiro, Rio de Janeiro, Brazil * Military Institute of Engineering, Rio de Janeiro, Brazil
(S) Clock Distribution Strategy for IP-based Development Rui L. Aguiar, Dinis M. Santos Aveiro Univ., Dept. of Electronics and Telecommunications, Aveiro, Portugal
An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures David H. Albonesi University of Rochester, Rochester, NY, USA
Chairs: Odysseas Koufopavlou, Univ. Patras, Greece J. Soares Augusto, IST/INESC, Portugal A Virtual CMOS Library Approach for Fast Prototyping F. Moraes +, M. Robert *, D. Auvergne * + Faculty of Informatics, PUC-RS, Porto Alegre, Brazil * LIRMM, CNRS/Univ. Montpellier II/CNRS, Montpellier, FranceRT-level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime Ananth Durbha, Srinivas Katkoori Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA
(S) Designing a Mask Programmable Matrix for Sequential Circuits Fernanda Lima, Marcelo Johann, José Güntzel, Eduardo D'Avila, Luigi Carro, Ricardo Reis Federal Univ. of Rio Grande do Sul, Institute of Informatics, Porto Alegre, RS, Brasil
(S) Placement Benchmarks for 3-D VLSI Stefan Thomas Obenaus +, Ted H. Szymanski * + School of Computer Science, McGill University, Montreal, Quebec, Canada * Communications Research Laboratory, McMaster University, Canada
Invited Substrate Noise: Analysis, Models and Optimization Edoardo Charbon +, Joel Phillips * + Cadence Design Systems, San Jose, CA, U.S.A. * Cadence Berkeley Laboratories, Berkeley, CA, U.S.A.
Chairs: George Milne, Univ. of South Australia, Australia. António Ferrari, INESC/Aveiro, Aveiro Univ., Portugal Scalable Run Time Reconfigurable Architecture Abdellah Touhafi, Wouter Brissinck and Erik Dirkx Vrije Universiteit Brussel, Brussel, BelgiumFrontier: A Fast Placement System For FPGAs Russell Tessier University of Massachusetts, Amherst, MA, USA
Dynamically Reconfigurable Implementation of Control Circuits Nuno Lau, Valery Sklyarov Dept. of Electronics and Telecommunications, Aveiro Univ., Portugal
Chairs: João Paulo Teixeira, IST/INESC, Portugal Marios Papaefthymiou, U. of Michigan, Ann Arbor, MI, U.S.A. History-Based Dynamic Minimization during BDD Construction Rolf Drechsler, Wolfgang Gunther Institute of Computer Science, Albert-Ludwigs University, Freiburg, GermanyAuraII: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems Luca P. Carloni +, Evguenii I. Goldberg *, Tiziano Villa %, Robert K. Brayton +, Alberto L. Sangiovanni-Vincentelli + + Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, CA, U.S.A. * Cadence Berkeley Laboratories, berkeley, CA, U.S.A. % PARADES, Rome, Italy
Satisfiability-Based Functional Delay Fault Testing Joonyoung Kim +, João Marques-Silva*b , Karem Sakallah + + Univ. of Michigan, Ann Arbor, MI, U.S.A. * IST/INESC, Lisboa, Portugal
(S): Short paper presentation