QUAD-LOGIC

Bibliographic References

[1] Gupta, A.K.; Dally, W.J., "Topology optimization of interconnection networks," Computer Architecture Letters , vol.5, no.1, pp.10-13, Jan.-June 2006.
[2] Banerjee, K.; Souri, S.J.; Kapur, P.; Saraswat, K.C., "3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proceedings of the IEEE , vol.89, no.5, pp.602-633, May 2001.
[3] B. Havemann, ``The interconnect challenge'' 16th Biennial University Government Industry Microelectronics Symposium June 2006.
[4] R. Pragasan, ``Spartan FPGA - The Gate Array Solution'' Xilinx Application Notes, Aug. 2001.
[5] Fei Li, Yan Lin and Lei He, ``Power Modeling and characteristics of Field Programmable Gate Arrays''. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, n. 11, nov. 2005.
[6] A. Singh and M. Marek-Sadowska, ``Efficient Circuit Clustering for. Area and Power Reduction in FPGAs''. FPGA, Feb. 2002.
[7] Xilinx, ``The Programmable Logic Databook 2003''. Xilinx Inc., San Jose, California, 2003.
[8] E. Dubrova. ``Multiple-Valued Logic in VLSI: Challenges and Opportunities''. In: Proc. NORCHIP, 1999, pp 340-350. 1999.
[9] T-S. Jung et al. ``A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications''. IEEE J. Solid-State Circuits 31, 11, 1996, pp 1575-1583. 1996.
[10] A. F. Gonzalez, P. Mazumder, ``Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices''. IEEE trans. on Computers, 47, 9, 1998, pp 947-959. 1998.
[11] T. Hanyu, M. Kameyana. ``A 200MHz Pipelined Multiplier Using 1.5V-Supply Multiple-valued MOS Current-Mode Circuits With Dual-Rail Source-Coupled Logic''. IEEE J. of Solid-State Circuits. 30, 11, 1995, pp 1239-1245. 1995.
[12] Z. Zilic and Z.G. Vranesic, ``Multiple-Valued Logic in FPGAs'', Proc. 36th Midwest Symp. on Circuits and Systems, Detroit, Mi., Aug. 1993.
[13] A. Sheikholeslami, R. Yoshimura, P.G. Gulak. ``Look-up tables (LUTs) for multiple-valued, combinational logic'', Proc. of ISMVL 98, pp 264-269. 1998.
[14] R.C.G Silva. H. Boudinov, L. Carro. ``A novel Voltage-mode CMOS quaternary logic design''. IEEE Trans. Elec. Devices, v. 53-6, June, 2006.
[15] R.C.G Silva. H. Boudinov, L. Carro. ``Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design''. 37th International Symposium on Multiple-Valued Logic, 2007. pp. 56-62. 2007.
[16] R.C.G Silva. C. Lazzari, H. Boudinov, L. Carro. ``CMOS vaoltage-mode quaternary look-up tables for multi-valued FPGAs''. Submitted to IET Computer \& Digital Systems.
[17] M. Gao et al. ``Optimization of Multi-Valued Multi-Level Networks''. Proceedings of the International Symposium on Multiple-Valued Logic, 2002.
[18] T. Luba. ``Decomposition of Multiple-valued Functions''. Proceedings of the ISMVL 1995. pp 256-261. 1995.
[19] S. Sinha, S. Khatri, R. Brayton, A. Sangiovanni-Vincentelli. ``Binary and Multi-valued SPFD-based Wire Removal in PLA Networks''. Proceedings of the ICCD. 2000. pp 494-503. 2000.
[20] R. Dreschsler, M. Thornton, D. Wessels. ``MDD-Based Synthesis of Multi-Valued logic Networks''. Proceedings of the ISMVL 2000. pp 41-46. 2000.
[21] C. Files, R. Drechsler, M. Perkowski. ``Functional Decomposition of MVL Functions using Multi-valued Decision Diagrams''. Proc. of the ISMVL. 1997. pp 27-32. 1997.
[22] R. K. Brayton, S. P. Khatri, ``Multi-valued Logic Synthesis'', International Conference on VLSI Design, 1999.
[23] Synopsys. ``HSPICE Electric Simulation''. www.hspice.com/.
[24] A. Mishchenko, R. Brayton. ``A Boolean Paradigm in Multi-valued Logic Synthesis''. In the Notes of the International Workshop on Logic Synthesis, New Orleans, June 2002.
[25] A. Mishchenko, R. Brayton. ``Simplification of Non-Deterministic Multi-Valued Networks''. IEEE/ACM International Conference on CAD, ICCAD 02, Santa Clara, November 2002.
[26] J.H. Jiang, A. Mishchenko, R. Brayton. ``Reducing Multi-Valued Algebraic Operations to Binary''. Design Automation and Test in Europe, DATE 2003.
[27] Y. Yasuda. et al. ``Realization of quaternary logic circuits by n-channel MOS devices''. IEEE Journal of Solid-State Circuits. vol. SC-21. n 1, pp. 162-168, Feb. 1986.
[28] S. Park. et al. ``Design of quaternary logic gate using double pass-transistor logic with neuron MOS down literal circuit''. Proceedings of the 34th International Symposium on Multiple-Valued Logic, 2004. pp. 198-203. 2004.
[29] I. Thoidis, et al. ``Quaternary voltage-mode CMOS circuits for multiple-valued logic''. Proceedings of the Circuits, Devices and Systems. pp. 71-77, April 1998.

Past Publications

Cristiano Lazzari and Thiago Assis and Fernanda Kastensmidt and Gilson Wirth and Ricardo Reis and Lorena Anghel, An Analysis and Design Technique to Reduce SET Sensitivity in Combinational Integrated Circuits, 16th IFIP/IEEE International Conference on VLSI-Soc, Oct. 2008 , pp. 114-117 .
Paulo Flores and Horacio Claudio Campos Neto and Joao Marques Silva, An exact solution to the minimum-size test pattern problem, ACM Transactions on Design Automation of Electronic Systems (TODAES), 6(4), pp. 629-644, Oct. 2001,
Eduardo Cesar da Costa and Segio Bampi and J. Monteiro, Power Optimization Using Coding Methods on Arithmetic Operators, IEEE International Symposium on Signals, Circuits and Systems, Jul. 2001 , pp. 505-508.
J. Monteiro and Arlindo L. Oliveira, Implicit FSM Decomposition Applied To Low Power Design, IEEE Transactions on Very Large Scale Integration Systems, 10(5), pp. 560-565, Oct. 2002, IEEE Press.
J. Monteiro, R. Patel, V. Tiwari, Power Analysis and Optimization from Circuit to Register-Transfer Levels}, book chapter in EDA for IC Implementation, Circuit Design And Process Technology, editors G. Martin, L. Lavagno, L. Scheffer, CRC Press, March 2006.