Q-FPGA -
High Speed Power-efficient Voltage-mode Quaternary Programmable Circuits

Project Reference: PTDC/EEA-ELC/121509/2010

 

Past Publications

Project team past 5 references, last updated Mon Feb 28 0:19:24 2011

refA  refA.pdf Cristiano Lazzari, Paulo Flores, José Monteiro, and Luigi Carro. "Voltage-mode quaternary FPGAs: An evaluation of interconnections". In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pages 869–972, May 30–June 2, 2010. (doi:10.1109/ISCAS.2010.5537423)
refB  refB.pdf Cristiano Lazzari, Paulo Flores, José Monteiro, and Luigi Carro. "A new quaternary FPGA based on a voltage-mode multi-valued circuit". In Proceedings of IEEE/ACM Design, Automation and Test in Europe Conference (DATE), pages 1797–1802, March 8–12, 2010.
refC  refC.pdf Cristiano Lazzari, Jorge Fernandes, Paulo Flores, and José Monteiro. "An efficient low power multiple-value look-up table targeting quaternary FPGAs". In International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 6448 of LNCS, pages 84–93, September 7–10, 2010. (doi:10.1007/978-3-642-17752-1_9)
refD  refD.pdf R. C. G. Silva, C. Lazzari, H. Boudinov, and L. Carro. "Cmos voltage-mode quaternary look-up tables for multi-valued fpgas". Microelectronics Journal, 40:1466–1470, October 2009. (doi:10.1016/j.mejo.2009.07.001)
refE  refE.pdf Marcus Ritt, Carlos Arthur Lang Lisboa, Luigi Carro, and Cristiano Lazzari. "A cost-effective technique for mapping bluts to qluts in fpgas". International Conference on Field Programmable Logic and Applications, pages 332–335, September 2010. (doi:10.1109/FPL.2010.72)

Bibligraphic References

List of refrences used on the "Literature Review" section. The 27 references, last updated Mon Feb 28 0:21:11 2011

ref01  ref01.pdf A.K. Gupta and W.J. Dally. "Topology optimization of interconnection networks". Computer Architecture Letters, 5(1):10–13, Jan.-June 2006. (doi:10.1109/L-CA.2006.8)
ref02  ref02.pdf K. Banerjee, S.J. Souri, P. Kapur, and K.C. Saraswat. "3-d ics: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration". Proceedings of the IEEE, 89(5):602–633, May 2001. (doi:10.1109/5.929647)
ref03  ref03.pdf B. Havemann. "The interconnect challenge", June 2006.
ref04  ref04.pdf Xilinx Application Notes. "Spartan FPGA - The Gate Array Solution", August 2001.
ref05  ref05.pdf Fei Li, Y. Lin, Lei He, Deming Chen, and J. Cong. "Power modeling and characteristics of field programmable gate arrays". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,, 24(11):1712 – 1724, November 2005. (doi:10.1109/TCAD.2005.852293)
ref06  ref06.pdf Amit Singh and Malgorzata Marek-Sadowska. "Efficient circuit clustering for area and power reduction in fpgas". In Proceedings of the 2002 ACM/SIGDA Tenth International Symposium on Field-Programmable Gate Arrays, FPGA '02, pages 59–66. ACM, February 2002. (doi:10.1145/503048.503058)
ref07  ref07.pdf R. C. G. Silva, C. Lazzari, H. Boudinov, and L. Carro. "Cmos voltage-mode quaternary look-up tables for multi-valued fpgas". Microelectronics Journal, 40:1466–1470, October 2009. (doi:10.1016/j.mejo.2009.07.001)
ref08  ref08.pdf Elena Dubrova. "Multiple-valued logic in vlsi: Challenges and opportunities". In In Proceedings of NORCHIP'99, pages 340–250, 1999.
ref09  ref09.pdf R. Cunha G. Silva, H. Boudinov, and L. Carro. "Quaternary look-up tables using voltage-mode cmos logic design". In Multiple-Valued Logic, 2007. ISMVL 2007. 37th International Symposium on, pages 56–62, May 2007. (doi:10.1109/ISMVL.2007.47)
ref10  ref10.pdf R.K. Brayton and S.P. Khatri. "Multi-valued logic synthesis". In VLSI Design, 1999. Proceedings. Twelfth International Conference On, pages 196–205, January 1999. (doi:10.1109/ICVD.1999.745148)
ref11  ref11.pdf R. Drechsler, M. Thornton, and D. Wessels. "Mdd-based synthesis of multi-valued logic networks". In Multiple-Valued Logic, 2000. (ISMVL 2000) Proceedings. 30th IEEE International Symposium on, pages 41–46, May 2000. (doi:10.1109/ISMVL.2000.848598)
ref12  ref12.pdf C. Files, R. Drechsler, and M. Perkowski. "Functional decomposition of mvl functions using multi-valued decision diagrams". In Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, pages 27–32, May 1997. (doi:10.1109/ISMVL.1997.601370)
ref13  ref13.pdf M. Gao, J.-H. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, T. Villa, and Brayton R. "Optimization of multi-valued multi-level networks". In Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on, pages 168–177, May 2002. (doi:10.1109/ISMVL.2002.1011086)
ref14  ref14.pdf A.F. Gonzalez and P. Mazumder. "Multiple-valued signed digit adder using negative differential resistance devices". IEEE Transactions on Computers, 47(9):947–959, September 1998. (doi:10.1109/12.713314)
ref15  ref15.pdf T. Hanyu and M. Kameyama. "A 200 mhz pipelined multiplier using 1.5 v-supply multiple-valued mos current-mode circuits with dual-rail source-coupled logic". IEEE Journal of Solid-State Circuits, 30(11):1239–1245, November 1995. (doi:10.1109/4.475711)
ref16  ref16.pdf J.-H.R. Jiang, A. Mischenko, and R.K. Brayton. "Reducing multi-valued algebraic operations to binary". In Design, Automation and Test in Europe Conference and Exhibition, 2003, pages 752 – 757, March 2003. (doi:10.1109/DATE.2003.1253697)
ref17  ref17.pdf Tae-Sung Jung, Young-Joon Choi, Kang-Deog Suh, Byung-Hoon Suh, Jin-Ki Kim, Young-Ho Lim, Yong-Nam Koh, Jong-Wook Park, Ki-Jong Lee, Jung-Hoon Park, Kee-Tae Park, Jhang-Rae Kim, Jeong-Hyong Yi, and Hyung-Kyu Lim. "A 117-mm2 3.3-v only 128-mb multilevel nand flash memory for mass storage applications". IEEE Journal of Solid-State Circuits, 31(11):1575–1583, November 1996. (doi:10.1109/JSSC.1996.542301)
ref18  ref18.pdf T. Luba. "Decomposition of multiple-valued functions". In Multiple-Valued Logic, 1995. Proceedings., 25th International Symposium on, pages 256–261, May 1995. (doi:10.1109/ISMVL.1995.513540)
ref19  ref19.pdf Alan Mishchenko and Robert K. Brayton. "A boolean paradigm in multi-valued logic synthesis". In the Notes of the International Workshop on Logic Synthesis, June 2002.
ref20  ref20.pdf A. Mishchenko, S. Chatterjee, and R.K. Brayton. "Improvements to technology mapping for lut-based fpgas". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,, 26(2):240–253, February 2007. (doi:10.1109/TCAD.2006.887925)
ref21  ref21.pdf Soo Jin Park, Byoung Hee Yoon, Kwang Sub Yoon, and Heung Soo Kim. "Design of quaternary logic gate using double pass-transistor logic with neuron mos down literal circuit". In Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on, pages 198 – 203, May 2004. (doi:10.1109/ISMVL.2004.1319941)
ref23  ref23.pdf R.C.G. Silva, H. Boudinov, and L. Carro. "A novel voltage-mode cmos quaternary logic design". IEEE Transactions on Electron Devices, 53(6):1480 – 1483, June 2006. (doi:10.1109/TED.2006.874751)
ref24  ref24.pdf S. Sinha, S.P. Khatri, R.K. Brayton, and A.L. Sangiovanni-Vincentelli. "Binary and multi-valued spfd-based wire removal in pla networks". In Proceedings of International Conference on Computer Design, pages 494–503, September 2000. (doi:10.1109/ICCD.2000.878328)
ref22  ref22.pdf Synopsys. "Hspice electric simulation". www.hspice.com.
ref25  ref25.pdf I. Thoidis, D. Soudris, I. Karafyllidis, S. Christoforidis, and A. Thanailakis. "Quaternary voltage-mode cmos circuits for multiple-valued logic". IEE Proceedings of Circuits, Devices and Systems, 145(2):71–77, April 1998. (doi:10.1049/ip-cds:19981763)
ref26  ref26.pdf Y. Yasuda, Y. Tokuda, S. Zaima, K. Pak, T. Nakamura, and A. Yoshida. "Realization of quaternary logic circuits by n-channel mos devices". IEEE Journal of Solid-State Circuits, 21(1):162 – 168, February 1986. (doi:10.1109/JSSC.1986.1052493)
ref27  ref27.pdf Z. Zilic and Z.G. Vranesic. "Multiple-valued logic in fpgas". In Proceedings of the 36th Midwest Symposium on Circuits and Systems, pages 1553 –1556 vol.2, August 1993. (doi:10.1109/MWSCAS.1993.343412)