The main goal of this research project is the development of new models and algorithms for optimization of Multiple Constant Multiplications (MCM) architectures. Most of existing algorithms simply minimize the number of adders and subtracters used in MCM blocks. However, the total delay of MCM blocks is also an important requirement that has been ignored in most optimization models. The developed algorithms should incorporate area and delay in a common optimization model for MCM blocks and be tuned for each MCM instance in order to reduce the total problem search space. Moreover, in this project new architectures targeting different requirements will be proposed and evaluated. Dedicated architectures for low-power consumption that trade-off computation speed (throughput) with power consumption will be studied. The propose architectures should have the capability to activate only the hardware elements of the MCM that are required for computation of a given constant multiplication. By reducing the global switching activity in the MCM, major saving in power consumption are expected. As an outcome of the research project, a set of tools, adequate for integration in a typical design flow and incorporating the developed optimization algorithms for specific architectures, will be made available as open software in a public webpage of the project.