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-Configurable Logic Block Cell for Quaternary FPGAs (IE02035) (Project Link)
Acronym: QCell
Paulo Ferreira Godinho Flores
From 01-Apr-2013 to 31-Mar-2014
Prime Contractor: INESC-ID (Other)
Financed by: FCT (Other)
Partnerships: INESC-ID (Other)
Members: Paulo Ferreira Godinho Flores, Jorge Manuel dos Santos Ribeiro Fernandes, Josť Carlos Alves Pereira Monteiro


The goal of this exploratory project is to develop new quaternary programmable control logic block (QCLB) that is suitable to be used as a core cell in quaternary FPGAs and is able to efficiently implement the most common circuits. A quaternary lookup table (QLUT) should be designed and optimized regarding its area, delay and power consumption. Extra circuitry should also be include in the QCLB in order to efficiently implement most common circuits (e.g., adders, multipliers, registers, etc). Moreover, in this project we will also design, manufacture and test a prototype chip with the developed QCLBs programmed to implement some simple operations. We also plan to fully characterize the QCLB circuit, with exhaustive electrical simulation, and check the computed values against the real results obtained from the prototype chip.
This project involves two different research groups from INESC-ID: ALGOS - Algorithms for Optimization and Simulation, and AMSC - Analog and Mixed-Signal Circuits. The ALGOS and the AMSC groups teams have a wide experience on analog and digital circuit design, namely on the development of new circuit architectures, circuit synthesis and power optimization.