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-An Environment for the Design and Analysis of Power Efficient Systems (IE02015)
Acronym: CoolChips
Josť Carlos Alves Pereira Monteiro
From 01-Jan-2000 to 31-Dec-2005
Prime Contractor: INESC-ID (Other)
Financed by: FCT (Other)
Partnerships: INESC-ID (Other)
Members: Ana Teresa Correia de Freitas, Arlindo Manuel Limede de Oliveira, Josť Carlos Alves Pereira Monteiro, Josť Carlos Campos Costa, Lino Josť Baeta Pinchete, Luis Miguel Teixeira D Avila Pinto da Silveira


The objective of this project is to develop a framework for low power design at the system level. The focus will be on optimizing architectures for low power at the register-transfer level (RTL), and on techniques for ultra low-power core microprocessors both in terms of hardware and software. At the RTL, a few particular designs with well defined behavior, such as FFT and FIR filters, will be implemented using different architectures. From the comparison of their power performance a methodology will be developed. Encoding in the system buses will be essayed both for RTL and microprocessor design, and the asymmetry of operands exploited in hardware and software. Memory system optimization will also be addressed. Power estimation tools will be developed to allow the evaluation of different alternatives at each design abstraction level. An RTL tool based on macromodels will be implemented that accounts for word level correlations, and uses models that include interconnect capacitance.