ALGOS Logo

Paulo Ferreira Godinho Flores
Senior Researcher
 
phone: +351-213100399
Ext.: 2399
Fax INESC: +351-213145843
E-mail: pff@inesc-id.pt
Home Page: http://algos.inesc.pt/~pff
 
 
 
Publications
International Journal Articles
-Levent Aksoy and Paulo Flores and J. Monteiro, A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures, Circuits, Systems and Signal Processing, (), pp. 1-31, Jan. 2014, Springer. [bibTeX]
 
-Nuno Sebastião and Nuno Roma and Paulo Flores, Configurable and Scalable Class of High Performance Hardware Accelerators for Simultaneous DNA Sequence Alignment, Journal on Concurrency and Computation: Practice & Experience, 25(10), pp. 1319–1339, Jun. 2013, Wileys. [DOI link] [bibTeX]
 
-Levent Aksoy and Cristiano Lazzari and Eduardo Costa and Paulo Flores and J. Monteiro, Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 21(3), pp. 498-511, Mar. 2013, . [bibTeX]
 
-Nuno Sebastião and Nuno Roma and Paulo Flores, Integrated Hardware Architecture for Efficient Computation of the n-Best Bio-Sequence Local Alignments in Embedded Platforms, IEEE Transactions on Very Large Scale Integration Systems, 20(7), pp. 1262-1275, Jul. 2012, IEEE. [DOI link] [bibTeX]
 
-Levent Aksoy and Cristiano Lazzari and Eduardo Costa and Paulo Flores and J. Monteiro, High-Level Algorithms for the Optimization of Gate-Level Area in Digit-Serial Multiple Constant Multiplications, Integration, the VLSI Journal, 45(3), pp. 294–306, Jun. 2012, Elsevier. [bibTeX]
 
-Nuno Sebastião and Nuno Roma and Paulo Flores, Hardware Accelerator Architecture for Simultaneous Short-Read DNA Sequences Alignment with Enhanced Traceback Phase, Microprocessors and Microsystems, 36(2), pp. 96-109, Mar. 2012, Elsevier. [DOI link] [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Optimization Algorithms for the Multiplierless Realization of Linear Transforms, ACM Transactions on Design Automation of Electronic Systems (TODAES), 17(1), pp. 3:1-3:27, Jan. 2012, . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Finding the Optimal Tradeoff Between Area and Delay in Multiple Constant Multiplications, Elsevier Journal on Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), 35(8), pp. 729-741, Nov. 2011, . [bibTeX]
 
-Cristiano Lazzari and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and J. Monteiro, An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 6448(), pp. 84-93, Oct. 2011, . [bibTeX]
 
-Cristiano Lazzari and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and J. Monteiro, Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays, Journal of Low Power Electronics, 7(2), pp. 294-301, Apr. 2011, American Scientific Publishers. [bibTeX]
 
-Levent Aksoy and Ece Olcay Gunes and Paulo Flores, Search algorithms for the multiple constant multiplications problem: Exact and approximate, Microprocessors and Microsystems, Embedded Hardware Design (MICPRO), 34(5), pp. 151-162, Mar. 2010, Elsevier B.V.. [DOI link] [bibTeX]
 
-Pedro Marques Morgado and Paulo Flores and L. Miguel Silveira, Generating Realistic Stimuli for Accurate Power Grid Analysis, ACM Transactions on Design Automation of Electronic Systems, 14(3), pp. 4-66, May. 2009, ACM. [bibTeX]
 
-Luis Filipe Colaço Messias Gil and Paulo Flores and L. Miguel Silveira, PMSat: a parallel version of MiniSAT, Journal on Satisfiability, Boolean Modeling and Computation, 6(), pp. 71-98, Sep. 2008, . Supplementary Material [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(6), pp. 1013 - 1026, Jun. 2008, IEEE. [DOI link] [bibTeX]
 
-Paulo Flores and Horácio C. Neto and Joao Marques Silva, An exact solution to the minimum-size test pattern problem, ACM Transactions on Design Automation of Electronic Systems (TODAES), 6(4), pp. 629-644, Oct. 2001, . [bibTeX]
 
 
International Conferences
-Levent Aksoy and Paulo Flores and J. Monteiro, Towards the Least Complex Time-Multiplexed Constant Multiplication, 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2013 , pp. 328-331 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Exploration of Tradeoffs in the Design of Integer Cosine Transforms for Image Compression, 21st European Conference on Circuit Theory and Design (ECCTD), Sep. 2013 , pp. 1-4 . [bibTeX]
 
-Nuno Neves and Nuno Sebastião and André Patrício and David Martins de Matos and Pedro Tomás and Paulo Flores and Nuno Roma, BioBlaze: Multi-Core SIMD ASIP for DNA Sequence Alignment, International Conference on Application-specific Systems, Architectures and Processors (ASAP 2013), Jun. 2013 , pp. 241-244 , IEEE. [bibTeX]
 
-Diogo Rodrigues Oliveira de Brito and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and J. Monteiro, Standard CMOS Voltage-Mode QLUT Using a Clock Boosting Technique, 11th IEEE International NEWCAS Conference, Jun. 2013 . [bibTeX]
 
-Ricardo Sousa Marques and Luis Guerra e Silva and Paulo Flores and L. Miguel Silveira, Improving sat solver efficiency using a multi-core approach, International Florida Artificial Intelligence Research Society Conference (FLAIRS), May. 2013 , pp. 94-99 . [bibTeX]
 
-Levent Aksoy and Paulo Flores and J. Monteiro, SIREN: A Depth-First Algorithm for the Filter Design Optimization Problem, Great Lakes Symposium on VLSI (GLSVLSI), May. 2013 , pp. 179-184 . [bibTeX]
 
-Diogo Rodrigues Oliveira de Brito and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and J. Monteiro, Design and Characterization of a QLUT in a Standard CMOS Process, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec. 2012 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Multiple Tunable Constant Multiplications: Algorithms and Applications, International Conference on Computer-Aided Design (ICCAD), Nov. 2012 , pp. 473-479 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs, Design Automation and Test in Europe (DATE), Mar. 2012 , pp. 1197-1202 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, A Hybrid Algorithm for the Optimization of Area and Delay in Linear DSP Transforms, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2011 , pp. 148-153 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Optimization of Gate-Level Area in High Throughput Multiple Constant Multiplications, European Conference on Circuit Theory and Design (ECCTD), Aug. 2011 , pp. 588-591 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Design of Low-Power Multiple Constant Multiplications Using Low-Complexity Minimum Depth Operations, Great Lakes Symposium on VLSI (GLSVLSI), May. 2011 , pp. 79-84 . [bibTeX]
 
-Levent Aksoy and Cristiano Lazzari and Eduardo Costa and Paulo Flores and J. Monteiro, Efficient Shift-Adds Design of Digit-Serial Multiple Constant Multiplications, Great Lakes Symposium on VLSI (GLSVLSI), May. 2011 , pp. 61-66 . [bibTeX]
 
-Levent Aksoy and Cristiano Lazzari and Eduardo Costa and Paulo Flores and J. Monteiro, Optimization of Area in Digit-Serial Multiple Constant Multiplications at Gate-Level, IEEE International Symposium on Circuits and Systems (ISCAS), May. 2011 , pp. 2737-2740 . [bibTeX]
 
-Cristiano Lazzari and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and J. Monteiro, An Efficient Low Power Multiple-Value Look-up Table Targeting Quaternary FPGAs, International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS’10) , Sep. 2010 . [bibTeX]
 
-Diego Jaccottet and Eduardo Costa and Levent Aksoy and Paulo Flores and J. Monteiro, Design of Low-Complexity and High-Speed Digital Finite Impulse Response Filters, International Conference on VLSI and System on Chip (VLSI-SoC), Sep. 2010 , pp. 292-297 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications, Euromicro Conference on Digital System Design , Aug. 2010 , pp. 3-10 . [bibTeX]
 
-Nuno Sebastião and Tiago Dias and Nuno Roma and Paulo Flores, Integrated Accelerator Architecture for DNA Sequences Alignment with Enhanced Traceback Phase, International Conference on High Performance Computing & Simulation (HPCS 2010), Jun. 2010 , pp. 16-23 . [bibTeX]
 
-Cristiano Lazzari and Paulo Flores and J. Monteiro and Luigi Carro, Voltage-mode Quaternary FPGAs: An Evaluation of Interconnections, IEEE International Symposium on Circuits and Systems (ISCAS 2010), May. 2010 , pp. 869-872 , IEEE France Section. [bibTeX]
 
-Cristiano Lazzari and Paulo Flores and J. Monteiro and Luigi Carro, A New Quaternary FPGA Based on a Voltage-mode Multi-valued Circuits, Design, Automation & Test in Europe (DATE 2010), Mar. 2010 , pp. 1797 - 1802 . [bibTeX]
 
-Cristiano Lazzari and Paulo Flores and J. Monteiro, Power and Delay Comparison of Binary and Quaternary Arithmetic Circuits, IEEE International Conference on Signals, Circuits and Systems (SCS’09), Nov. 2009 . [bibTeX]
 
-Levent Aksoy and Ece Olcay Gunes and Paulo Flores, Optimization of area under a delay constraint in multiple constant multiplications, International Conference on Circuits (ICC), Jul. 2009 , pp. 81-86 , World Scientific and Engineering Academy and Society. [bibTeX]
 
-Fábio Daitx and Vagner S. Rosa and Eduardo Costa and Paulo Flores and Sérgio Bampi, VHDL generation of optimized FIR filters, International Conference on Signals, Circuits and Systems (SCS), Nov. 2008 , pp. 1-5 . [bibTeX]
 
-Levent Aksoy and Ece Olcay Gunes and Paulo Flores, An exact breadth-first search algorithm for the multiple constant multiplications problem, NORCHIP, Nov. 2008 , pp. 41-46 . [bibTeX]
 
-Nuno Sebastião and Tiago Dias and Nuno Roma and Paulo Flores and Leonel Sousa, Application specific programmable IP core for motion estimation: technology comparison targeting efficient embedded co-processing units, 11th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools - DSD2008, Sep. 2008 , pp. 181-188 , IEEE Computer Society. [bibTeX]
 
-P. Marques Morgado and Paulo Flores and J. Monteiro and L. Miguel Silveira, Generating Worst-case Stimuli for Accurate Power Grid Analysis, International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sep. 2008 , pp. z z . [bibTeX]
 
-Nuno Sebastião and Tiago Dias and Nuno Roma and Paulo Flores and Leonel Sousa, Specialized Motion Estimation Processor for Heterogeneous Multicore Video Coding Systems, 4th International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems - ACACES2008, Jul. 2008 , pp. 63-66 , HiPEAC. [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Ece Gunes and Paulo Flores and J. Monteiro, Effect of Number Representation on the Achievable Minimum Number of Operations, IEEE Workshop on Signal Processing Systems (SiPS), Oct. 2007 , pp. 424-429 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Minimum Number of Operations under a General Number Representation for Digital Filter Synthesis, Proceedings of the European Conference on Circuit Theory and Design (ECCTD), Aug. 2007 , pp. 252-255 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Optimization of Area in Digital FIR Filters using Gate-Level Metrics, IEEE/ACM Design Automation Conference (DAC), Jun. 2007 , pp. 420-423 . [bibTeX]
 
-Pedro Marques Morgado and Paulo Flores and L. Miguel Silveira, Generating Realistic Stimuli for Accurate Power Grid Analysis, IEEE International Symposium on VLSI, May. 2007 , IEEE Press. [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec. 2006 . [bibTeX]
 
-Eduardo Costa and Paulo Flores and J. Monteiro, Exploiting General Coefficient Representation for the Optimal Exploiting Sharing of Partial Products in MCMs, IEEE XIX Symposium on Integrated Circuits and Systems Design, Aug. 2006 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Optimization of Area Under a Delay Constraint in Digital Filter Synthesis Using SAT-Based Integer Linear Programming, IEEE/ACM Design Automation Conference (DAC), Jul. 2006 , pp. 669-674 . [bibTeX]
 
-Paulo Flores and J. Monteiro and Eduardo Costa, An Exact Algorithm for the Maximal Sharing of Partial Terms in Multiple Constant Multiplications, International Conference on Computed Aided Design (ICCAD), Nov. 2005 , pp. 13-16 , ACM/IEEE. [bibTeX]
 
-Eduardo Costa and Paulo Flores and J. Monteiro, Maximal Sharing of Partial Terms in MCM under Minimal Signed Digit Representation, European Conference on Circuit Theory and Design (ECCTD), Sep. 2005 , pp. 221-224 , IEEE. [bibTeX]
 
-Paulo Flores and Horácio C. Neto and Krishnendu Chakrabarty and Joao Marques Silva, Test Pattern Generation for Width Compression in BIST, IEEE International Symposium on Circuits and Systems (ISCAS), May. 1999 , pp. 114-118 . [bibTeX]
 
-Paulo Flores and Horácio C. Neto and Joao Marques Silva, On Applying Set Covering Models to Test Set Compaction, IEEE Great Lakes Symposium on VLSI (GLS), Mar. 1999 , pp. 8-11 . [bibTeX]
 
-Paulo Flores and José Carlos Campos Costa and Horácio C. Neto and J. Monteiro and Joao Marques Silva, Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation, IEEE/ACM International Conference on VLSI Design (VLSI), Jan. 1999 , pp. 37-41 . [bibTeX]
 
-Paulo Flores and Horácio C. Neto and Joao Marques Silva, An Exact Solution to the Minimum-Size Test Pattern Problem, IEEE International Conference on Computer Design (ICCD), Oct. 1998 , pp. 510-515 . [bibTeX]
 
-Paulo Flores and Horácio C. Neto and Joao Marques Silva, An Exact Solution to the Minimum-Size Test Pattern Problem, IEEE/ACM International Workshop on Logic Synthesis (IWLS, Jul. 1998 , pp. 452-470 . [bibTeX]
 
-Paulo Flores and Horácio C. Neto and Krishnendu Chakrabarty and Joao Marques Silva, A Model and Algorithm for Computing Minimum-Size Test Patterns, IEEE European Test Workshop (ETW), May. 1998 , pp. 147-148 . [bibTeX]
 
-José Carlos Campos Costa and Paulo Flores and Horácio C. Neto and J. Monteiro and Joao Marques Silva, Exploiting Don't Cares in Test Patterns to Reduce Power During BIST, IEEE European Test Workshop, May. 1998 . [bibTeX]
 
-Vasco Manquinho and Paulo Flores and Joao Marques Silva and Arlindo L. Oliveira, Prime implicant computation using satisfiability algorithms, 9th IEEE International Conference on Tools with Artificial Intelligence, Nov. 1997 , pp. 232--239 , IEEE. [bibTeX]
 
 
National Conferences
-José Cabrita and Gilberto Rodrigues and Paulo Flores, Hardware accelerator for biological sequence alignment using coreworks® processing engine, Jornadas sobre Sistemas Reconfiguráveis (REC), Feb. 2013 , pp. 83-88 . [bibTeX]
 
-Nuno Sebastião and Nuno Roma and Paulo Flores, Scalable Accelerator Architecture for Local Alignment of DNA Sequences, VI Jornadas sobre Sistemas Reconfiguráveis - REC2010, Feb. 2010 , pp. 59-66 , Universidade de Aveiro / IEETA. [bibTeX]
 
-Tiago Dias and Nuno Sebastião and Nuno Roma and Paulo Flores and Leonel Sousa, Programmable IP core for motion estimation: comparison of FPGA and ASIC based implementations, IV Jornadas sobre Sistemas Reconfiguráveis - REC2008, Feb. 2008 , pp. 109-116 . [bibTeX]
 
 
Technical Reports
-Ana Isabel Feliciano Gomes and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores, Quaternary Logic Look-Up Table: an Alternative Circuit, INESC-ID Tec. Rep. 2/2014, Feb 2014. [bibTeX]
 
-Ricardo Sousa Marques and Luis Guerra e Silva and Paulo Flores and L. Miguel Silveira, Improving SAT Solver Efficiency using a Cooperative Multicore Approach, INESC-ID Tec. Rep. 28/2012, Oct 2012. [bibTeX]
 
-Ricardo Sousa Marques and Luis Guerra e Silva and Paulo Flores and L. Miguel Silveira, cmcSAT - A Cooperative MultiCore SAT Solver, INESC-ID Tec. Rep. 20/2012, Jul 2012. [bibTeX]
 
-Nuno Sebastião and Nuno Roma and Paulo Flores, Insertion and Improvement of Testability Mechanisms on a Specialized Multimedia IP Core, INESC-ID Tec. Rep. 32/2009, May 2009. [bibTeX]
 
-L. Miguel Silveira and Jorge F. Villena and Paulo Flores and G. Ciuprina and D. Mihalache and D. Ioan and W.H.A. Schilders and N.v.d. Meijs and K-J.v.d. Kolk, CHAMELEON RF D3.4 - Report on Issues and Guidelines for Coupled Circuit and Parasitic Analysis, INESC-ID Tec. Rep. 65/2008, Apr 2008. [bibTeX]
 
-L. Miguel Silveira and Jorge F. Villena and Paulo Flores and G. Ciuprina and D. Ioan and D. Niculae and A. Stefanescu and R. Janssen and W.H.A. Schilders and N.v.d. Meijs and K-J.v.d. Kolk and E. Seebacher and W. Pflanzl, CHAMELEON RF D3.1 - Report on Parametric Model Order Reduction Techniques, INESC-ID Tec. Rep. 34/2007, May 2007. [bibTeX]
 
-Paulo Flores and J. Monteiro and Eduardo Costa, Maximal Sharing of Partial Terms in Multiple Constant Multiplications: Analysis of an Exact Algorithm, INESC-ID Tec. Rep. 14/2005, Apr 2005. [bibTeX]
 
-Paulo Flores and Horácio C. Neto and Joao Marques Silva, On Computing Minimum Size Test Patterns, INESC-ID Tec. Rep. 8/2000, Nov 2000. [bibTeX]
 
 
PhD Theses
-Paulo Flores, Models and Algorithms for Optimization Problems in Digital Circuits Testing, PhD Thesis, IST, Dec 2001 . [bibTeX]
 
 
Book Chapters
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, VLSI-SoC: Advanced Research for Systems on Chip, Chapter Multiplierless Design of Linear DSP Transforms, Jun 2012, Springer. [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Advanced Topics in VLSI Design, Chapter Optimization Algorithms for Multiple Constant Multiplications, Jan 2009, . [bibTeX]
 
-João M. S. Silva and Jorge F. Villena and Paulo Flores and L. Miguel Silveira, Scientific Computing in Electrical Engineering, Chapter Outstanding Issues in Model Order Reduction, May 2007, Springer Berlin Heidelberg. [bibTeX]
 
 
Other Publications
-Ricardo Sousa Marques and Luis Guerra e Silva and Paulo Flores and L. Miguel Silveira, pmcSAT[bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Multicon - Multiplierless Design of Low-Complexity and High-Speed DSP Systems[bibTeX]
 
-Fábio F. Daitx and Eduardo Costa and Paulo Flores and Sergio Bampi, Uma ferramenta para geração automática de VHDL para filtros FIR otimizados[bibTeX]
 
 
National Patents
-Jorge Manuel dos Santos Ribeiro Fernandes and Cristiano Lazzari and Paulo Flores and J. Monteiro, Tabela Multi-Valor para Dispositivos Lógicos Programáveis, Pat. No. 2147483647, Pedido Provisório de Patente - INPI [bibTeX]
 
 
 
 
Finished Projects
-Hardware accelerator for biological sequences alignment (IE02031)
Acronym: Sidework Biocores
Paulo Ferreira Godinho Flores
From ??-Jan-2009 to ??-Sep-2012
Prime Contractor: INESC-ID (Other)
Financed by: QREN (Other) - Lisbon, Portugal
Partnerships: Coreworks (Company) - Lisboa, Portugal
Members: Paulo Ferreira Godinho Flores

The main objectives of this project/task is the hardware implementation ... (more...)
 
-Architectural Optimization of DSP Systems with Multiple Constants Multiplications (IE02030) (Project Link)
Acronym: Multicon
Paulo Ferreira Godinho Flores
From 01-Jan-2009 to 31-Jul-2012
Prime Contractor: INESC-ID (Other)
Financed by: FCT (Other)
Partnerships: INESC-ID (Other)
Members: Paulo Ferreira Godinho Flores, José Carlos Alves Pereira Monteiro, Levent Aksoy

The main goal of this research project is the development of new models ... (more...)
 
-Parallel Satisfiability Algorithms and its Applications (IE02032) (Project Link)
Acronym: ParSat
Paulo Ferreira Godinho Flores
From 04-Apr-2010 to 04-Apr-2013
Prime Contractor: INESC-ID (Other)
Financed by: FCT (PTDC/EIA-EIA/103532/2008) (Other) -Portugal
Partnerships: INESC-ID (Other)
Members: Paulo Ferreira Godinho Flores, José Carlos Alves Pereira Monteiro, Luís Jorge Brás Monteiro Guerra e Silva, Luis Miguel Teixeira D Avila Pinto da Silveira, Maria Inês Camarate de Campos Lynce de Faria, Vasco Miguel Gomes Nunes Manquinho

The Boolean Satisfiability Problem (SAT) is a fundamental problem in com... (more...)
 
-Configurable Logic Block Cell for Quaternary FPGAs (IE02035) (Project Link)
Acronym: QCell
Paulo Ferreira Godinho Flores
From 01-Apr-2013 to 31-Mar-2014
Prime Contractor: INESC-ID (Other)
Financed by: FCT (Other)
Partnerships: INESC-ID (Other)
Members: Paulo Ferreira Godinho Flores, Jorge Manuel dos Santos Ribeiro Fernandes, José Carlos Alves Pereira Monteiro

The goal of this exploratory project is to develop new quaternary progra... (more...)