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José Carlos Alves Pereira Monteiro
Senior Researcher
 
phone: +351-213100283
Ext.: 2283
Fax INESC: +351-213145843
E-mail: jcm@inesc-id.pt
Home Page: http://algos.inesc-id.pt/~jcm
 
 
 
Publications
International Journal Articles
-Levent Aksoy and Paulo Flores and J. Monteiro, A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures, Circuits, Systems and Signal Processing, (), pp. 1-31, Jan. 2014, Springer. [bibTeX]
 
-José Carlos Campos Costa and J. Monteiro, Coverage-Directed Observability-Based Validation for Embedded Software, ACM Transactions on Design Automation of Electronic Systems (TODAES), 18(2), pp. 19:1-19:20, Mar. 2013, . [bibTeX]
 
-Levent Aksoy and Cristiano Lazzari and Eduardo Costa and Paulo Flores and J. Monteiro, Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 21(3), pp. 498-511, Mar. 2013, . [bibTeX]
 
-João Bispo and João M. P. Cardoso and J. Monteiro, Hardware Pipelining of Repetitive Patterns in Processor Instruction Traces, Journal of Integrated Circuits and Systems, 8(1), pp. 22-31, Mar. 2013, . [bibTeX]
 
-Levent Aksoy and Cristiano Lazzari and Eduardo Costa and Paulo Flores and J. Monteiro, High-Level Algorithms for the Optimization of Gate-Level Area in Digit-Serial Multiple Constant Multiplications, Integration, the VLSI Journal, 45(3), pp. 294–306, Jun. 2012, Elsevier. [bibTeX]
 
-Carlos Manuel Boura Sampaio and J. Monteiro and L. Miguel Silveira, Analysis of the Conditions for the Worst Case Switching Activity in Integrated Circuits, Analog Integrated Circuits and Signal Processing, 70(2), pp. 229-240, Feb. 2012, Springer. [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Optimization Algorithms for the Multiplierless Realization of Linear Transforms, ACM Transactions on Design Automation of Electronic Systems (TODAES), 17(1), pp. 3:1-3:27, Jan. 2012, . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Finding the Optimal Tradeoff Between Area and Delay in Multiple Constant Multiplications, Elsevier Journal on Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), 35(8), pp. 729-741, Nov. 2011, . [bibTeX]
 
-Cristiano Lazzari and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and J. Monteiro, An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 6448(), pp. 84-93, Oct. 2011, . [bibTeX]
 
-Cristiano Lazzari and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and J. Monteiro, Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays, Journal of Low Power Electronics, 7(2), pp. 294-301, Apr. 2011, American Scientific Publishers. [bibTeX]
 
-L. Pieper and Eduardo Costa and S. Bampi and J. Monteiro, Efficient Dedicated Multiplication Blocks for 2´s Complement Radix-16 and Radix-256 Array Multipliers, Journal of Computers, 5(10), pp. 1502-1509, Oct. 2010, Academy Publisher. [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(6), pp. 1013 - 1026, Jun. 2008, IEEE. [DOI link] [bibTeX]
 
-Eduardo Costa and J. Monteiro and S. Bampi, A New Regular Array Architecture for Signed Radix-2^m Multiplication, Integration: the VLSI Journal, 40(2), pp. 118-132, Jan. 2007, Elsevier Science Publishers. [bibTeX]
 
-José Carlos Campos Costa and L. Miguel Silveira and Srinivas Devadas and J. Monteiro, Power Estimation Using Probability Polynomials, Design Automation for Embedded Systems, 9(1), pp. 19-52, Mar. 2004, Spriger-Verlag. [bibTeX]
 
-J. Monteiro and Arlindo L. Oliveira, Implicit FSM Decomposition Applied To Low Power Design, IEEE Transactions on Very Large Scale Integration Systems, 10(5), pp. 560-565, Oct. 2002, IEEE Press. Article [DOI link] [bibTeX]
 
-J. Monteiro and S. Devadas, Power Estimation under User-Specified Input Sequences and Programs, Integrated Computer-Aided Engineering, 5(2), pp. 177-185, Oct. 1998, IOS Press. [bibTeX]
 
-J. Monteiro and Srinivas Devadas and Abhijit Ghosh, Sequential Logic Optimization for Low Power Using Input-Disabling Precomputation Architectures, IEEE Transactions on Computer-Aided Design, 17(3), pp. 279-284, Mar. 1998, IEEE Press. [bibTeX]
 
-J. Monteiro and S. Devadas and A. Ghosh and K. Keutzer and J. White, Estimation of Average Switching Activity in Combinational Logic Circuits Using Symbolic Simulation, IEEE Transactions on Computer-Aided Design, 16(1), pp. 121-127, Jan. 1997, IEEE Press. [bibTeX]
 
-J. Monteiro and S. Devadas, Techniques for Power Estimation and Optimization at the Logic Level: A Survey, Journal of VLSI Signal Processing Systems, 13(2), pp. 259-276, Aug. 1996, Kluwer Academic Publishers. [bibTeX]
 
-J. Monteiro and S. Devadas and A. Ghosh, Retiming Sequential Circuits for Low Power, International Journal of High Speed Electronics and Systems, 7(2), pp. 323-340, Jun. 1996, World Scientific Publishing. [bibTeX]
 
-C-Y. Tsui and J. Monteiro and M. Pedram and S. Devadas and A. Despain and B. Lin, Power Estimation Methods for Sequential Logic Circuits, IEEE Transactions on VLSI Systems, 3(3), pp. 404-416, Sep. 1995, IEEE Press. [bibTeX]
 
-M. Alidina and J. Monteiro and S. Devadas and A. Ghosh and M. Papaefthymiou, Precomputation-Based Sequential Logic Optimization for Low Power, IEEE Transactions on VLSI Systems, 2(2), pp. 426-436, Dec. 1994, IEEE Press. [bibTeX]
 
 
International Conferences
-Nuno Claudino Pereira Lopes and J. Monteiro, Weakest Precondition Synthesis for Compiler Optimizations, 15th International Conference on Verification, Model Checking, and Abstract Interpretation (VMCAI), Jan. 2014 . [bibTeX]
 
-Levent Aksoy and Paulo Flores and J. Monteiro, Towards the Least Complex Time-Multiplexed Constant Multiplication, 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2013 , pp. 328-331 . [bibTeX]
 
-L. Pieper and Eduardo Costa and J. Monteiro, Combination of Radix-2^m Multiplier Blocks and Adder Compressors for the Design of Efficient 2's Complement 64-bit Array Multipliers, 26th Symposium on Integrated Circuits and System Design, Sep. 2013 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Exploration of Tradeoffs in the Design of Integer Cosine Transforms for Image Compression, 21st European Conference on Circuit Theory and Design (ECCTD), Sep. 2013 , pp. 1-4 . [bibTeX]
 
-Nuno Claudino Pereira Lopes and J. Monteiro, Automatic Equivalence Checking of UF+IA Programs, International SPIN Symposium on Model Checking of Software - SPIN13, Jul. 2013 . [bibTeX]
 
-Diogo Rodrigues Oliveira de Brito and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and J. Monteiro, Standard CMOS Voltage-Mode QLUT Using a Clock Boosting Technique, 11th IEEE International NEWCAS Conference, Jun. 2013 . [bibTeX]
 
-Levent Aksoy and Paulo Flores and J. Monteiro, SIREN: A Depth-First Algorithm for the Filter Design Optimization Problem, Great Lakes Symposium on VLSI (GLSVLSI), May. 2013 , pp. 179-184 . [bibTeX]
 
-Diogo Rodrigues Oliveira de Brito and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and J. Monteiro, Design and Characterization of a QLUT in a Standard CMOS Process, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec. 2012 . [bibTeX]
 
-S. Ghissoni and Eduardo Costa and J. Monteiro and R. Reis, Efficient Area and Power Multiplication Part of FFT Based on Twiddle Factor Decomposition, 19th IEEE International Conference on Electronics, Circuits and Systems – ICECS2012, Dec. 2012 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Multiple Tunable Constant Multiplications: Algorithms and Applications, International Conference on Computer-Aided Design (ICCAD), Nov. 2012 , pp. 473-479 . [bibTeX]
 
-João Bispo and João Cardoso and J. Monteiro, Hardware Pipelining of Runtime-Detected Loops, IEEE XXV Symposium on Integrated Circuits and Systems Design (SBCCI), Sep. 2012 , pp. 1-6 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs, Design Automation and Test in Europe (DATE), Mar. 2012 , pp. 1197-1202 . [bibTeX]
 
-S. Ghissoni and Eduardo Costa and J. Monteiro and R. Reis, Combination of Constant Matrix Multiplication and Gate-level Approaches for Area and Power Efficient Hybrid Radix-2 DIT FFT Realization, 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec. 2011 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, A Hybrid Algorithm for the Optimization of Area and Delay in Linear DSP Transforms, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2011 , pp. 148-153 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Optimization of Gate-Level Area in High Throughput Multiple Constant Multiplications, European Conference on Circuit Theory and Design (ECCTD), Aug. 2011 , pp. 588-591 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Design of Low-Power Multiple Constant Multiplications Using Low-Complexity Minimum Depth Operations, Great Lakes Symposium on VLSI (GLSVLSI), May. 2011 , pp. 79-84 . [bibTeX]
 
-Levent Aksoy and Cristiano Lazzari and Eduardo Costa and Paulo Flores and J. Monteiro, Efficient Shift-Adds Design of Digit-Serial Multiple Constant Multiplications, Great Lakes Symposium on VLSI (GLSVLSI), May. 2011 , pp. 61-66 . [bibTeX]
 
-L. Oliveira and G. Dessbesell and J. Martins and J. Monteiro, Hardware Implementation of a Centroid-based Localization Algorithm for Mobile Sensor Networks, IEEE International Symposium on Circuits and Systems (ISCAS), May. 2011 . [bibTeX]
 
-Levent Aksoy and Cristiano Lazzari and Eduardo Costa and Paulo Flores and J. Monteiro, Optimization of Area in Digit-Serial Multiple Constant Multiplications at Gate-Level, IEEE International Symposium on Circuits and Systems (ISCAS), May. 2011 , pp. 2737-2740 . [bibTeX]
 
-S. Ghissoni and Eduardo Costa and Cristiano Lazzari and J. Monteiro and Levent Aksoy and R. Reis, Radix-2 Decimation in Time (DIT) Implementation Based on a Matrix-Multiple Constant Multiplication Approach, 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Dec. 2010 . [bibTeX]
 
-Cristiano Lazzari and Jorge Manuel dos Santos Ribeiro Fernandes and Paulo Flores and J. Monteiro, An Efficient Low Power Multiple-Value Look-up Table Targeting Quaternary FPGAs, International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS’10) , Sep. 2010 . [bibTeX]
 
-L. Oliveira and G. Dessbesell and J. Martins and J. Monteiro, CentroidM: a Centroid-based Localization Algorithm for Mobile Sensor Networks, IEEE XXIII Symposium on Integrated Circuits and Systems Design (SBCCI), Sep. 2010 . [bibTeX]
 
-Diego Jaccottet and Eduardo Costa and Levent Aksoy and Paulo Flores and J. Monteiro, Design of Low-Complexity and High-Speed Digital Finite Impulse Response Filters, International Conference on VLSI and System on Chip (VLSI-SoC), Sep. 2010 , pp. 292-297 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications, Euromicro Conference on Digital System Design , Aug. 2010 , pp. 3-10 . [bibTeX]
 
-Cristiano Lazzari and Paulo Flores and J. Monteiro and Luigi Carro, Voltage-mode Quaternary FPGAs: An Evaluation of Interconnections, IEEE International Symposium on Circuits and Systems (ISCAS 2010), May. 2010 , pp. 869-872 , IEEE France Section. [bibTeX]
 
-Cristiano Lazzari and Paulo Flores and J. Monteiro and Luigi Carro, A New Quaternary FPGA Based on a Voltage-mode Multi-valued Circuits, Design, Automation & Test in Europe (DATE 2010), Mar. 2010 , pp. 1797 - 1802 . [bibTeX]
 
-Carlos Manuel Boura Sampaio and J. Monteiro and L. Miguel Silveira, Analysis of the Conditions for Worst Case Switching Activity in Integrated Circuits, IEEE Latin American Symposium on Circuits and Systems (LASCAS), Feb. 2010 . [bibTeX]
 
-Cristiano Lazzari and Paulo Flores and J. Monteiro, Power and Delay Comparison of Binary and Quaternary Arithmetic Circuits, IEEE International Conference on Signals, Circuits and Systems (SCS’09), Nov. 2009 . [bibTeX]
 
-José Carlos Campos Costa and J. Monteiro, Observability-based Coverage-directed Path Search using PBO for Automatic Test Vector Generation, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2009 . [bibTeX]
 
-António Gusmão and L. Miguel Silveira and J. Monteiro, Power Macro-Modelling using an Iterative LS-SVM Method, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2009 . [bibTeX]
 
-S. Ghissoni and J. Martins and R. Reis and J. Monteiro, Analysis of Power Consumption using a New Methodology for the Capacitance Modeling of Complex Logic Gates, International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sep. 2009 . [bibTeX]
 
-José Carlos Campos Costa and J. Monteiro, A MILP-based Approach to Path Sensitization of Embedded Software, IEEE Design, Automation and Test in Europe (DATE), Apr. 2009 . [bibTeX]
 
-António Gusmão and L. Miguel Silveira and J. Monteiro, Parameter Tuning in SVM-Based Power Macro-Modeling, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2009 , pp. 135-140 , IEEE. [bibTeX]
 
-L. Pieper and Eduardo Costa and S. Bampi and J. Monteiro, Efficient Dedicated Multiplication Blocks for 2´s Complement Radix-16 and Radix-256 Array Multipliers, International Conference on Signals, Circuits & Systems (SCS08), Nov. 2008 . [bibTeX]
 
-P. Marques Morgado and Paulo Flores and J. Monteiro and L. Miguel Silveira, Generating Worst-case Stimuli for Accurate Power Grid Analysis, International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sep. 2008 , pp. z z . [bibTeX]
 
-José Carlos Campos Costa and J. Monteiro, Computation of the Minimal Set of Paths for Observability-Based Statement Coverage, 15th International Conference Mixed Design of Integrated Circuits and Systems, Jun. 2008 . [bibTeX]
 
-Rui Miguel Manteigas Cameira de Sousa e Rodrigues and J. Monteiro, Review of the Algorithm Selection, Eighth International Conference on Artificial Intelligence and Soft Computing, Jun. 2008 . [bibTeX]
 
-L. Pieper and Eduardo Costa and S. Almeida and S. Bampi and J. Monteiro, Efficient Dedicated Structures for the Radix-16 Multiplication, XIV Iberchip, Feb. 2008 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Ece Gunes and Paulo Flores and J. Monteiro, Effect of Number Representation on the Achievable Minimum Number of Operations, IEEE Workshop on Signal Processing Systems (SiPS), Oct. 2007 , pp. 424-429 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Minimum Number of Operations under a General Number Representation for Digital Filter Synthesis, Proceedings of the European Conference on Circuit Theory and Design (ECCTD), Aug. 2007 , pp. 252-255 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Optimization of Area in Digital FIR Filters using Gate-Level Metrics, IEEE/ACM Design Automation Conference (DAC), Jun. 2007 , pp. 420-423 . [bibTeX]
 
-Rudolfo Santos and J. Monteiro, Foot Fingerprints, IADIS International Conference on Applied Computing, Feb. 2007 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis, IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec. 2006 . [bibTeX]
 
-Eduardo Costa and Paulo Flores and J. Monteiro, Exploiting General Coefficient Representation for the Optimal Exploiting Sharing of Partial Products in MCMs, IEEE XIX Symposium on Integrated Circuits and Systems Design, Aug. 2006 . [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Optimization of Area Under a Delay Constraint in Digital Filter Synthesis Using SAT-Based Integer Linear Programming, IEEE/ACM Design Automation Conference (DAC), Jul. 2006 , pp. 669-674 . [bibTeX]
 
-Paulo Flores and J. Monteiro and Eduardo Costa, An Exact Algorithm for the Maximal Sharing of Partial Terms in Multiple Constant Multiplications, International Conference on Computed Aided Design (ICCAD), Nov. 2005 , pp. 13-16 , ACM/IEEE. [bibTeX]
 
-J. Monteiro and Jorge Manuel dos Santos Ribeiro Fernandes and L. Miguel Silveira, A Case for a Triangular Waveform Clock Signal, VLSI-SoC'2005 - IFIP International Conference on Very Large Scale Integration, Oct. 2005 , pp. 72-77 . [bibTeX]
 
-L. Oliveira and C. Santos and D. Ferrão and E. Costa and J. Monteiro and J. Martins and S. Bampi and R. Reis, A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures, VLSI-SoC'2005 - IFIP International Conference on Very Large Scale Integration, Oct. 2005 , pp. 78-82 . [bibTeX]
 
-M. Fonseca and E. Costa and S. Bampi and J. Monteiro, Design of a Radix-2^n Hybrid Array Multiplier Using Carry Save Adders, IEEE XVIII Symposium on Integrated Circuits and Systems Design, Sep. 2005 , pp. 221-224 . [bibTeX]
 
-Eduardo Costa and Paulo Flores and J. Monteiro, Maximal Sharing of Partial Terms in MCM under Minimal Signed Digit Representation, European Conference on Circuit Theory and Design (ECCTD), Sep. 2005 , pp. 221-224 , IEEE. [bibTeX]
 
-V. Rosa and S. Bampi and E. Costa and J. Monteiro, Performance Evaluation of Parallel FIR Filter Optimizations in ASICs and FPGA, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2005), Aug. 2005 . [bibTeX]
 
-M. Fonseca and E. Costa and S. Bampi and J. Monteiro, Performance Optimization of Radix-2^n Multipliers using Carry Save Adders, Iberchip, Mar. 2005 . [bibTeX]
 
-V. Rosa and E. Costa and S. Bampi and J. Monteiro, An Improved Synthesis Method for Low Power Hardwired FIR Filters, XVII Symposium on Integrated Circuits and Systems Design, Sep. 2004 , pp. 237-241 . [bibTeX]
 
-L. Oliveira and E. Costa and S. Bampi and J. Martins and J. Monteiro, Array Hybrid Multiplier versus Modified Booth Multiplier: Comparing Area and Power Consumption of Layout Implementations, IEEE International Midwest Symposium on Circuits and Systems, Jul. 2004 , pp. II213-II216 . [bibTeX]
 
-E. Costa and S. Bampi and J. Monteiro, Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths, IFIP VLSI-SOC, Dec. 2003 , pp. 307-312 . [bibTeX]
 
-E. Costa and S. Bampi and J. Monteiro, Low Power Architectures for FFT and FIR Dedicated Datapaths, IEEE Midwest Symposium on Circuits & Systems, Dec. 2003 . [bibTeX]
 
-José Carlos Campos Costa and J. Monteiro, Input Generation for Path Coverage in Software Testing, IEEE Workshop on Compilers and Tools for Constrained Embedded Systems, Oct. 2003 . [bibTeX]
 
-E. Costa and S. Bampi and J. Monteiro, A New Pipelined Array Architecture for Signed Multiplication, IEEE XVI Symposium on Integrated Circuits and Systems Design, Sep. 2003 , pp. 65-70 . [bibTeX]
 
-J. Portela and E. Costa and J. Monteiro, Optimal Combination of Number of Taps and Coefficient Bit-Width for Low Power FIR Filter Realization, IEEE European Conference on Circuit Theory and Design, Sep. 2003 , pp. 145-148 . [bibTeX]
 
-E. Costa and S. Bampi and J. Monteiro, A New Architecture for 2's Complement Gray Encoded Array Multiplier, IEEE XV Symposium on Integrated Circuits and Systems Design, Sep. 2002 , pp. 14-19 . [bibTeX]
 
-E. Costa and S. Bampi and J. Monteiro, A New Architecture for Signed Radix-2^m Pure Array Multipliers, IEEE International Conference on Computer Design, Sep. 2002 , pp. 112-117 . [bibTeX]
 
-E. Costa and S. Bampi and J. Monteiro, FIR Filter Design using Low Power Arithmetic Operators, IEEE Design and Diagnostics of Electronic Circuits and Systems, Apr. 2002 , pp. 314-317 . [bibTeX]
 
-E. Costa and S. Bampi and J. Monteiro, Power Efficient Arithmetic Operand Encoding, XIV Symposium on Integrated Circuits and Systems Design, Sep. 2001 , pp. 201-206 . [bibTeX]
 
-J. Portela and J. Monteiro, Power Optimized Viterbi Decoder Implementation through Architectural Transforms, XIV Symposium on Integrated Circuits and Systems Design, Sep. 2001 , pp. 212-217 . [bibTeX]
 
-Eduardo César da Costa and Ségio Bampi and J. Monteiro, Power Optimization Using Coding Methods on Arithmetic Operators, IEEE International Symposium on Signals, Circuits and Systems, Jul. 2001 , pp. 505-508 . [bibTeX]
 
-José Carlos Campos Costa and S. Devadas and J. Monteiro, Observability Analysis for Embedded Software in a Coverage-Directed Validation Methodology, IEEE/ACM International Conference on Computer-Aided Design, Nov. 2000 , pp. 27-32 . [bibTeX]
 
-J. Baptista and R. Reis and J. Monteiro, Capacitance and Power Modeling at the Logic Level, IFIP International Conference on Chip Design Automation, Aug. 2000 , pp. 203-210 . [bibTeX]
 
-R. Ferreira and A. M. Trullemans and José Carlos Campos Costa and J. Monteiro, Probabilistic Bottom-up RTL Power Estimation, IEEE/ACM International Symposium on Quality of Electronic Design, Mar. 2000 , pp. 439-446 . [bibTeX]
 
-J. Monteiro and Arlindo L. Oliveira, FSM Decomposition by Direct Circuit Manipulation Applied to Low Power Design, IEEE/ACM Asian and South Pacific Design Automation Conference, Jan. 2000 , pp. 351-358 . [bibTeX]
 
-A. S. Mota and N. M. Ferreira and Arlindo L. Oliveira and J. Monteiro, Integrating Dynamic Power Management in the Design Flow, X IFIP Conference on VLSI, Dec. 1999 , pp. 233--244 . [bibTeX]
 
-Ana T. Freitas and Arlindo L. Oliveira and J. Monteiro and Horácio C. Neto, Exact Power Estimation Using Word Level Transition Probabilities, IEEE International Workshop on Power and Timing Modelling, Optimization and Simulation, Oct. 1999 , pp. 355-364 . [bibTeX]
 
-José Carlos Campos Costa and J. Monteiro and L. Miguel Silveira and S. Devadas, A Probabilistic Approach for RT-Level Power Modeling, IEEE International Conference on Electronics, Circuits and Systems, Sep. 1999 , pp. 911-914 . [bibTeX]
 
-J. Monteiro, Power Optimization using Dynamic Power Management, XII Symposium on Integrated Circuits and Systems Design, Sep. 1999 , pp. 134-139 . [bibTeX]
 
-José Carlos Campos Costa and L. Miguel Silveira and J. Monteiro, Sequential Power Estimation using Probability Polynomials, IEEE International Symposium on Signals, Circuits and Systems,, Jul. 1999 , pp. 17-20 . [bibTeX]
 
-Paulo Flores and José Carlos Campos Costa and Horácio C. Neto and J. Monteiro and Joao Marques Silva, Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation, IEEE/ACM International Conference on VLSI Design (VLSI), Jan. 1999 , pp. 37-41 . [bibTeX]
 
-J. Monteiro, Techniques for Power Management at the Logic Level, IEEE International Conference on Electronics, Circuits and Systems, Sep. 1998 , pp. 2.181-2.184 . [bibTeX]
 
-J. Monteiro and Arlindo L. Oliveira, Finite State Machine Decomposition for Low Power, ACM/IEEE Design Automation Conference, Jun. 1998 , pp. 758--763 , ACM. [bibTeX]
 
-José Carlos Campos Costa and Paulo Flores and Horácio C. Neto and J. Monteiro and Joao Marques Silva, Exploiting Don't Cares in Test Patterns to Reduce Power During BIST, IEEE European Test Workshop, May. 1998 . [bibTeX]
 
-A. S. Mota and J. Monteiro and Arlindo L. Oliveira, Power Optimization of Combinational Modules using Self-timed Precomputation, IEEE International Symposium on Circuits and Systems, May. 1998 , pp. II.17-II.20 , IEEE. [bibTeX]
 
-José Carlos Campos Costa and J. Monteiro and S. Devadas, Switching Activity Estimation using Limited Depth Reconvergent Path Analysis, IEEE/ACM International Symposium on Low Power Electronics and Design, Aug. 1997 , pp. 184-189 . [bibTeX]
 
-J. Monteiro and Joao Marques Silva, Testability Analysis of Circuits using Data-Dependent Power Management, IX IFIP International Conference on Very Large Scale Integration, Aug. 1997 , pp. 353-364 . [bibTeX]
 
-Joao Marques Silva and J. Monteiro and K. Sakallah, Test Pattern Generation for Circuits Using Power Management Techniques, IEEE European Test Workshop, May. 1997 . [bibTeX]
 
-J. Monteiro and S. Devadas and P. Ashar and A. Mauskar, Scheduling Techniques to Enable Power Management, IEEE/ACM 33rd Design Automation Conference, Jun. 1996 , pp. 349-352 . [bibTeX]
 
-J. Monteiro and S. Devadas, Techniques for the Power Estimation of Sequential Logic Circuits Under User-Specified Input Sequences and Programs, IEEE/ACM International Symposium on Low Power Electronics and Design, Apr. 1995 , pp. 33-38 . [bibTeX]
 
-J. Monteiro and J. Rinderknecht and S. Devadas and A. Ghosh, Optimization of Combinational and Sequential Logic Circuits for Low Power Using Precomputation, Chapel Hill Conference on Advanced Research in VLSI, Mar. 1995 , pp. 430-444 . [bibTeX]
 
-M. Alidina and J. Monteiro and S. Devadas and A. Ghosh and M. Papaefthymiou, Precomputation-Based Sequential Logic Optimization for Low Power, IEEE/ACM International Conference on Computer-Aided Design, Nov. 1994 , pp. 74-81 . [bibTeX]
 
-J. Monteiro and S. Devadas and B. Lin, A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits, IEEE/ACM 31st Design Automation Conference, Jun. 1994 , pp. 12-17 . [bibTeX]
 
-J. Monteiro and J. Kukula and S. Devadas and Horácio C. Neto, Bitwise Encoding of Finite State Machines, IEEE 7th International Conference on VLSI Design, Jan. 1994 , pp. 379-382 . [bibTeX]
 
-J. Monteiro and S. Devadas and A. Ghosh, Retiming Sequential Circuits for Low Power, IEEE/ACM International Conference on Computer-Aided Design, Nov. 1993 , pp. 398-402 . [bibTeX]
 
 
National Conferences
-L. Pieper and Eduardo Costa and S. Almeida and S. Bampi and J. Monteiro, New Dedicated Architectures for the Radix-16 Multiplication, 23rd South Symposium on Microelectronics, May. 2008 . [bibTeX]
 
 
Technical Reports
-Nuno Claudino Pereira Lopes and Levent Aksoy and Vasco Manquinho and J. Monteiro, Optimally Solving the MCM Problem Using Pseudo-Boolean Satisfiability, INESC-ID Tec. Rep. 43/2010, Nov 2010. [bibTeX]
 
-Paulo Flores and J. Monteiro and Eduardo Costa, Maximal Sharing of Partial Terms in Multiple Constant Multiplications: Analysis of an Exact Algorithm, INESC-ID Tec. Rep. 14/2005, Apr 2005. [bibTeX]
 
-J. Monteiro and A. Mota, PCBIT Final Report, INESC-ID Tec. Rep. 3/2000, Feb 2000. [bibTeX]
 
 
PhD Theses
-J. Monteiro, A Computer-Aided Design Methodology for Low Power Sequential Logic Circuits, PhD Thesis, Massachusetts Institute of Technology, May 1996 . [bibTeX]
 
 
MSc Theses
-J. Monteiro, Codificação de Máquinas de Estados na Síntese Automática de Circuitos Lógicos, MSc Thesis, Instituto Superior Técnico, Jan 1993 . [bibTeX]
 
 
Books
-G. Arroz and J. Monteiro and Arlindo L. Oliveira, Arquitectura de Computadores: dos Sistemas Digitais aos Microprocessadores, Jul 2009, IST Press, 2nd Edition. [bibTeX]
 
-Guilherme S. Arroz and J. Monteiro and Arlindo L. Oliveira, Arquitectura de Computadores: dos Sistemas Digitais aos Microprocessadores, Jan 2007, IST Press. [bibTeX]
 
-J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Nov 1996, Kluwer Academic Publishers. [bibTeX]
 
 
Edited Books
-J. Monteiro and R. van Leuken Ed., Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, Lecture Notes in Computer Science, no. 5953, Feb 2010, Springer. [bibTeX]
 
-L. Svensson and J. Monteiro Ed., Integrated Circuit and System Design: Power and Timing Modeling Optimization and Simulation, Lecture Notes in Computer Science, no. 5349, Feb 2009, Springer. [bibTeX]
 
 
Book Chapters
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, VLSI-SoC: Advanced Research for Systems on Chip, Chapter Multiplierless Design of Linear DSP Transforms, Jun 2012, Springer. [bibTeX]
 
-António Gusmão and L. Miguel Silveira and J. Monteiro, VLSI-SoC: Technologies for Systems Integration, Chapter Power Macro-Modelling using an Iterative LS-SVM Method, Jun 2011, Springer. [bibTeX]
 
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Advanced Topics in VLSI Design, Chapter Optimization Algorithms for Multiple Constant Multiplications, Jan 2009, . [bibTeX]
 
-Rui Miguel Manteigas Cameira de Sousa e Rodrigues and J. Monteiro, Computational Intelligence: Methods and Applications, Chapter Review of the Algorithm Selection, Jun 2008, Exit Publishers. [bibTeX]
 
-L. Oliveira and Eduardo Costa and J. Monteiro and J. Martins and S. Bampi and C. Santos and D. Ferrão and R. Reis, VLSI-SoC: From Systems to Silicon, Chapter A Comparison of Layout Implementations of Pipelined And Non-Pipelined Signed Radix-4 Array Multiplier And Modified Booth Multiplier Architectures, Sep 2007, Springer. [bibTeX]
 
-Eduardo Costa and J. Monteiro and S. Bampi, VLSI-SOC: From Systems to Chips, Chapter Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths, May 2006, Springer. [bibTeX]
 
-J. Monteiro and V. Tiwari and P. Rakesh, EDA for IC Implementation, Circuit Design And Process Technology, Chapter Power Analysis and Optimization from Circuit to Register-Transfer Levels, Mar 2006, CRC Press. [bibTeX]
 
 
Other Publications
-Levent Aksoy and Eduardo Costa and Paulo Flores and J. Monteiro, Multicon - Multiplierless Design of Low-Complexity and High-Speed DSP Systems[bibTeX]
 
 
National Patents
-Jorge Manuel dos Santos Ribeiro Fernandes and Cristiano Lazzari and Paulo Flores and J. Monteiro, Tabela Multi-Valor para Dispositivos Lógicos Programáveis, Pat. No. 2147483647, Pedido Provisório de Patente - INPI [bibTeX]
 
 
Special Issues of Journals (editor)
-J. Monteiro Ed., , Journal of Low Power Electronics, (), Apr. 2010, . [bibTeX]
 
 
 
 
Finished Projects
-An Environment for the Design and Analysis of Power Efficient Systems (IE02015)
Acronym: CoolChips
José Carlos Alves Pereira Monteiro
From 01-Jan-2000 to 31-Dec-2005
Prime Contractor: INESC-ID (Other)
Financed by: FCT (Other)
Partnerships: INESC-ID (Other)
Members: Ana Teresa Correia de Freitas, Arlindo Manuel Limede de Oliveira, José Carlos Alves Pereira Monteiro, José Carlos Campos Costa, Lino José Baeta Pinchete, Luis Miguel Teixeira D Avila Pinto da Silveira

The objective of this project is to develop a framework for low power de... (more...)
 
-Convénio GRICES / CNPq (IE02019)
Acronym: GRICES
José Carlos Alves Pereira Monteiro
From 01-Jan-2006 to 01-Dec-2008
Prime Contractor: INESC-ID Lisboa (University) - Lisbon, Portugal
Financed by: FCT (Other)
Partnerships: Universidade Federal do Rio Grande do Sul (University) - Porto Alegre, RS, Brazil
Members: José Carlos Alves Pereira Monteiro



 
-International Workshop on Power and Timing Modelling, Optimization and Simulation (IE02029)
Acronym: PATMOS
José Carlos Alves Pereira Monteiro
From 01-Jul-2007 to 07-Dec-2008
Prime Contractor: INESC-ID (Other)
Financed by: Conference PATMOS (Other)
Members: José Carlos Alves Pereira Monteiro, Paulo Ferreira Godinho Flores, Marcelino Bicho dos Santos, João Manuel Paiva Cardoso, Luís Jorge Brás Monteiro Guerra e Silva, Luis Miguel Teixeira D Avila Pinto da Silveira

Organization of the above wokshop
 
-Consulting with Qualcomm Flarion Technologies (IE02034) (Project Link)
Acronym: Qualcomm
José Carlos Alves Pereira Monteiro
From 01-Jun-2012 to 31-Dec-2013
Prime Contractor: INESC-ID (Other)
Financed by: QUALCOMM (Company) -United States
Partnerships: INESC-ID (Other)
, QUALCOMM (Company) -United States
Members: José Carlos Alves Pereira Monteiro, Levent Aksoy, Paulo Ferreira Godinho Flores

The FlashLinQ and Lycan modems employ FIR filters within the signal proc... (more...)