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Luís Jorge Brás Monteiro Guerra e Silva
Senior Researcher
 
phone: +351-213100207
Ext.: 2207
Fax INESC: +351-213145843
E-mail: lgs@algos.inesc-id.pt
Home Page: http://algos.inesc-id.pt/~lgs
 
 
 
Publications
International Journal Articles
-Luis Guerra e Silva and Joel R. Phillips and L. Miguel Silveira, Effective Corner-Based Techniques for Variation-Aware IC Timing Verification, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(1), pp. 157-162, Jan. 2010, IEEE. [bibTeX]
 
-Joao Marques Silva and Luis Guerra e Silva, Solving Satisfiability in Combinational Circuits, IEEE Design and Test of Computers, (), pp. 16-21, Jul. 2003, IEEE Press. [bibTeX]
 
-Chandu Visweswariah and Luis Guerra e Silva and Andrew R. Conn, Exploiting Optimality Conditions in Accurate Static Circuit Tuning, High Performance Algorithms and Software for Nonlinear Optimization, (), pp. 356-374, Feb. 2003, Kluwer Academic Publishers. [bibTeX]
 
-Luis Guerra e Silva and Joao Marques Silva and L. Miguel Silveira and K. A. Sakallah, Satisfiability Models and Algorithms for Circuit Delay Computation, ACM Transactions on Design Automation of Electronic Systems, 7(1), pp. 137-158, Jan. 2002, . [bibTeX]
 
 
International Conferences
-Ricardo Sousa Marques and Luis Guerra e Silva and Paulo Flores and L. Miguel Silveira, Improving sat solver efficiency using a multi-core approach, International Florida Artificial Intelligence Research Society Conference (FLAIRS), May. 2013 , pp. 94-99 . [bibTeX]
 
-Luis Guerra e Silva and L. Miguel Silveira, Handling Intra-Die Variations in PSTA, ACM Great Lakes Symposium on VLSI, May. 2011 , pp. 403-406 . [bibTeX]
 
-Luis Guerra e Silva and Joel Phillips and L. Miguel Silveira, Speedpath Analysis Under Parametric Timing Models, ACM/IEEE Design Automation Conference, Jun. 2010 , pp. 268-273 . [bibTeX]
 
-Luis Guerra e Silva and L. Miguel Silveira and Joel Phillips, Efficient Computation of the Worst-Delay Corner, IEEE/ACM Design, Automation and Test in Europe Conference, Apr. 2007 . [bibTeX]
 
-Luis Guerra e Silva and Zhenhai Zhu and Joel R. Phillips and L. Miguel Silveira, Variation-Aware, Library Compatible Delay Modeling Strategy, VLSI-SoC 2006 - Proceedings of the 14th IFIP WG 10.5 International Conference on Very Large Scale Integration and System-on-Chip, Oct. 2006 , pp. 122-127 , IFIP. [bibTeX]
 
 
Technical Reports
-Ricardo Sousa Marques and Luis Guerra e Silva and Paulo Flores and L. Miguel Silveira, Improving SAT Solver Efficiency using a Cooperative Multicore Approach, INESC-ID Tec. Rep. 28/2012, Oct 2012. [bibTeX]
 
-Ricardo Sousa Marques and Luis Guerra e Silva and Paulo Flores and L. Miguel Silveira, cmcSAT - A Cooperative MultiCore SAT Solver, INESC-ID Tec. Rep. 20/2012, Jul 2012. [bibTeX]
 
 
PhD Theses
-Luis Guerra e Silva, Timing Analysis of Integrated Circuits Under Process Variations, PhD Thesis, Instituto Superior Técnico, Universidade Técnica de Lisboa, May 2009 (*). [bibTeX]
 
 
Book Chapters
-Luis Guerra e Silva and Zhenhai Zhu and Joel R. Phillips and L. Miguel Silveira, "VLSI-SoC: Research Trends in VLSI and Systems on Chip", Chapter "Library Compatible Variational Delay Computation", Jan 2008, Springer. [bibTeX]
 
 
Other Publications
-Ricardo Sousa Marques and Luis Guerra e Silva and Paulo Flores and L. Miguel Silveira, pmcSAT[bibTeX]